Renesas M16C/6NK Hardware Manual page 127

Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
BCLK
Address
CPU use
bus
RD signal
WR signal
Data
CPU use
bus
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address, or when the
transfer unit is 16 bits and an 8-bit bus is used
BCLK
Address
CPU use
bus
RD signal
WR signal
Data
CPU use
bus
(3) When the source read cycle under condition (1) has one wait state inserted
BCLK
Address
CPU use
bus
RD signal
WR signal
Data
CPU use
bus
(4) When the source read cycle under condition (2) has one wait state inserted
BCLK
Address
CPU use
bus
RD signal
WR signal
Data
CPU use
bus
NOTE:
1. The same timing changes occur with the respective conditions at the destination as at the source.
Figure 12.5 Transfer Cycles for Source Read
Rev.2.00 Nov 28, 2005
REJ09B0124-0200
Source Destination
Source
Source Source + 1
Source Source + 1
Source
Source
Source
Source
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Dummy
cycle
Dummy
Destination
cycle
Dummy
Destination
cycle
Dummy
Destination
cycle
Dummy
Destination
cycle
Dummy
Destination
cycle
Source + 1 Destination
Source + 1
12. DMAC
CPU use
CPU use
CPU use
CPU use
CPU use
CPU use
Dummy
CPU use
cycle
Dummy
Destination CPU use
cycle