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M16C/6N Group (M16C/6NK, M16C/6NM)
DMA1 Request Cause Select Register
b7
b6
b5
b4
b3
NOTE:
1. The causes of DMA1 requests can be selected by a combination of the DMS bit and the DSEL3 to DSEL0 bits
in the manner described below.
DSEL3 to DSEL0 Bits
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
DMAi Control Register (i = 0, 1)
b7
b6
b5
b4
b3
NOTES:
1.
The DMAS bit can be set to "0" by writing "0" in a program. (This bit remains unchanged even if "1" is written.)
2. At least one of the DAD and DSD bits must be "0" (address direction fixed).
Figure 12.3 DM1SL Register, DM0CON and DM1CON Registers
Rev.2.00
Nov 28, 2005
REJ09B0124-0200
b2
b1
b0
Symbol
DM1SL
Bit Symbol
DSEL0
DSEL1
DMA Request Cause
Select Bit
DSEL2
DSEL3
-
Nothing is assigned. When write, set to "0".
(b5-b4)
When read, their contents are "0".
DMA Request Cause
DMS
Expansion Select Bit
Software DMA
DSR
Request Bit
DMS = 0 (basic cause of request)
Falling edge of INT1 pin
Software trigger
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
UART0 transmit
UART0 receive/ACK0
UART2 transmit
UART2 receive/ACK2
A/D conversion
UART1 transmit/ACK1
b2
b1
b0
Symbol
DM0CON
DM1CON
Bit Symbol
Transfer Unit Bit
DMBIT
Select Bit
Repeat Transfer Mode
DMASL
Select Bit
DMAS
DMA Request Bit
DMAE
DMA Enable Bit
Source Address Direction
DSD
Select Bit
Destination Address
DAD
Direction Select Bit
-
Nothing is assigned. When write, set to "0".
(b7-b6)
When read, their contents are "0".
page 106 of 378
Address
After Reset
03BAh
00h
Bit Name
See NOTE 1
0 : Basic cause of request
1 : Extended cause of request
A DMA request is generated by setting
this bit to "1" when the DMS bit is "0"
(basic cause) and the DSEL3 to DSEL0
bits are "0001b" (software trigger).
The value of this bit when read is "0".
DMS = 1 (extended cause of request)
—
—
—
—
—
SI/O3
SI/O4
Two edges of INT1 pin
—
—
—
—
—
—
—
—
Address
After Reset
002Ch
00000X00b
003Ch
00000X00b
Bit Name
0 : 16 bits
1 : 8 bits
0 : Single transfer
1 : Repeat transfer
0 : DMA not requested
1 : DMA requested
0 : Disabled
1 : Enabled
0 : Fixed
(2)
1 : Forward
0 : Fixed
(2)
1 : Forward
Function
RW
RW
RW
RW
RW
-
RW
RW
Function
RW
RW
RW
RW
(1)
RW
RW
RW
-
12. DMAC
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