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M16C/6N Group (M16C/6NK, M16C/6NM)
Table 21.7 Pin Functions for Standard Serial I/O Mode
Pin
VCC1, VCC2, VSS
CNVSS
_____________
RESET
XIN
XOUT
BYTE
AVCC, AVSS
VREF
P0_0 to P0_7
P1_0 to P1_7
P2_0 to P2_7
P3_0 to P3_7
P4_0 to P4_7
P5_0
P5_1 to P5_4,
P5_6, P5_7
P5_5
P6_0 to P6_3
_________
P6_4/RTS1
P6_5/CLK1
P6_6/RXD1
P6_7/TXD1
P7_0 to P7_7
P8_0 to P8_3,
P8_6, P8_7
P8_4
_______
P8_5/NMI
P9_0 to P9_4, P9_7
P9_5/CRX0
P9_6/CTX0
P10_0 to P10_7
(3)
P11_0 to P11_7
(3)
P12_0 to P12_7
(3)
P13_0 to P13_7
(3)
P14_0, P14_1
NOTES:
1. When using the standard serial I/O mode, It is necessary to input "H" to the TXD1(P6_7) pin while the RESET pin
is "L". Therefore, the internal pull-up is enabled for the TXD1(P6_7) pin while the RESET pin is "L".
2. When using the standard serial I/O mode, the P0_0 to P0_7, P1_0 to P1_7 pins may become indeterminate
while the P8_4 pin is "H" and the RESET pin is "L". If this causes a problem, apply "L" to the P8_4 pin.
3. The pins P11 to P14 are only in the 128-pin version.
Rev.2.00
Nov 28, 2005
REJ09B0124-0200
Name
I/O
Apply the Flash Program, Erase Voltage to VCC1 pin and VCC2 to
Power supply
input
VCC2 pin. The VCC apply condition is that VCC2 = VCC1.
Apply 0 V to VSS pin.
CNVSS
Connect to VCC1 pin.
I
Reset input
I
Reset input pin. While RESET pin is "L" level, input 20 cycles or
longer clock to XIN pin.
Clock input
I
Connect a ceramic resonator or crystal oscillator between XIN and
XOUT pins. To input an externally generated clock, input it to XIN
Clock output
O
pin and open XOUT pin.
Connect this pin to VCC1 or VSS.
BYTE
I
Analog power
Connect AVCC to VCC1 and AVSS to VSS, respectively.
supply input
Reference
Enter the reference voltage for A/D and D/A converters from this
I
pin.
voltage input
Input port P0
Input "H" or "L" level signal or open.
I
Input "H" or "L" level signal or open.
Input port P1
I
Input port P2
Input "H" or "L" level signal or open.
I
Input port P3
Input "H" or "L" level signal or open.
I
Input "H" or "L" level signal or open.
Input port P4
I
_____
CE input
Input "H" level signal.
I
Input "H" or "L" level signal or open.
Input port P5
I
________
EPM input
Input "L" level signal.
I
Input port P6
Input "H" or "L" level signal or open.
I
BUSY output
Standard serial I/O mode 1: BUSY signal output pin
O
Standard serial I/O mode 2: Monitors the boot program operation
Standard serial I/O mode 1: Serial clock input pin.
SCLK input
I
Standard serial I/O mode 2: Input "L".
RXD input
Serial data input pin
I
Serial data output pin
TXD output
O
Input port P7
Input "H" or "L" level signal or open.
I
Input "H" or "L" level signal or open.
Input port P8
I
Input "L" level signal.
P8_4 input
I
________
NMI input
Connect this pin to VCC1.
I
Input port P9
Input "H" or "L" level signal or open.
I
Input "H" or "L" level signal or connect to a CAN transceiver.
CRX input
I
CTX output
Input "H" level signal, open or connect to a CAN transceiver.
O
Input "H" or "L" level signal or open.
Input port P10
I
Input port P11
Input "H" or "L" level signal or open.
I
Input "H" or "L" level signal or open.
Input port P12
I
Input "H" or "L" level signal or open.
Input port P13
I
Input port P14
Input "H" or "L" level signal or open.
I
____________
page 283 of 378
21. Flash Memory Version
Description
____________
check signal output pin.
(1)
(2)
____________
____________
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