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M16C/6N Group (M16C/6NK, M16C/6NM)
(1) Example of Transmit Timing (when internal clock is selected)
Transfer clock
"1"
TE bit in
UiC1 register
"0"
"1"
TI bit in
UiC1 register
"0"
"H"
CTSi
"L"
CLKi
TXDi
"1"
TXEPT bit in
UiC0 register
"0"
"1"
IR bit in
SiTIC register
"0"
The above timing diagram applies to the case where the register bits are set as follows:
CKDIR bit in UiMR register = 0 (internal clock)
CRD bit in UiC0 register = 0 (CTS/RTS enabled), CRS bit in UiC0 register = 0 (CTS selected)
CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock)
UiRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty):
U0IRS bit is bit 0 in UCON register
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
(2) Example of Receive Timing (when external clock is selected)
"1"
RE bit in
UiC1 register
"0"
"1"
TE bit in
UiC1 register
"0"
"1"
TI bit in
UiC1 register
"0"
"H"
RTSi
"L"
CLKi
RXDi
"1"
RI bit in
UiC1 register
"0"
IR bit in
"1"
SiRIC register
"0"
The above timing diagram applies to the case where the register bits are set
as follows:
CKDIR bit in UiMR register = 1 (external clock)
CRD bit in UiC0 register = 0 (CTS/RTS enabled), CRS bit = 1 (RTS selected)
CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive
fEXT: frequency of external clock
Figure 15.11 Transmit and Receive Operation
Rev.2.00
Nov 28, 2005
REJ09B0124-0200
TC
Write data to the UiTB register
Transferred from the UiTB register to the UARTi transmit register
TCLK
D0 D1 D2 D3 D4 D5 D6 D7
Set to "0" when interrupt request is accepted, or set to "0" in a program
Write dummy data to the UiTB register
Transferred from the UiTB register to the UARTi transmit register
1 / f
EXT
Receive data is taken in
D0 D1 D2 D3 D4 D5 D6 D7
Transferred from UARTi receive register
to the UiRB register
Set to "0" when interrupt request is
accepted, or set to "0" in a program
data taken in at the rising edge of the transfer clock)
page 162 of 378
Stopped pulsing because CTS
= H
i
D0 D1 D2 D3 D4 D5 D6 D7
TC = TCLK = 2(n + 1) / fj
fj: frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
n: value set to the UiBRG register
i = 0 to 2
Even if the reception is completed, the RTS
does not change. The RTS becomes "L"
when the RI bit changes to "0" from "1".
D0 D1 D2 D3 D4 D5
Read out from the UiRB register
Make sure the following conditions are met when input
to the CLKi pin before receiving data is high:
TE bit in UiC1 register = 1 (transmission enabled)
RE bit in UiC1 register = 1 (reception enabled)
Write dummy data to the UiTB register
15. Serial Interface
Stopped pulsing because the TE bit = 0
D0 D1 D2 D3 D4 D5 D6 D7
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