Renesas M16C/6NK Hardware Manual page 398

REVISION HISTORY
Rev. Date
Page
1.10 Jul. 01, 2005 212
223
228
230
232
272
273
274
307
–
2.00 Nov. 28, 2005
1
2
3
5
6
7, 8
9
10 to 12 Tables 1.6 to 1.8 Pin Characteristics in 128-pin version (1)(2)(3) are added.
13 to 15 Tables 1.8 to 1.10 Pin Description (1)(2)(3) are revised.
18
19
34
35 to 37 5. Reset: Layout is changed.
36
36
M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual
Figure 18.11 C0RECR, C1RECR Registers, C0TECR, C1TECR Registers, C0TSR,
C1TSR Registers, and C0AFS, C1AFS Registers
• C0RECR, C1RECR Registers: NOTE 2 is deleted.
• C0TECR, C1TECR Registers: NOTE 1 is deleted.
• C0TSR, C1TSR Registers: NOTE 1 is deleted.
18.15.1 Reception (1): "(refer to 18.15.2 Transmission)" is deleted.
Figure 19.1 I/O Ports (1): "P7_0" in 4th figure is deleted.
Figure 19.3 I/O Ports (3): "P7_0" is added to middle figure.
Figure 19.6 I/O Pins: NOTE 1 is deleted.
Table 21.4 Electrical Characteristics (1)
• Measuring Condition of V
Table 21.5 Electrical Characteristics (2): Mask ROM (5th item)
• "f(XCIN)" is changed to "(f(BCLK)).
Table 21.6 A/D Conversion Characteristics: "Tolerance Level Impedance" is deleted.
22.14 Programmable I/O Ports: last 1 to 2 lines
• (1) Setting Procedure is revised from "#00010000b" to "#00000001b".
• (2) Setting Procedure is revised from "#00010011b" to "#00110001b".
Revised edition issued
* Memory expansion and microprocessor modes are added to Normal-ver..
* Electric Characteristics of T/V-ver. is added.
* Revised parts and revised contents are as follows (except for expressional change).
1.1 Applications: Comment of T/V-ver. is added.
Table 1.1 Performance Outline (100-pin version): Operation Mode of Normal-ver. is revised.
Table 1.2 Performance Outline (128-pin version): Operation Mode of Normal-ver. is revised.
Table 1.3 Product List: NOTE 1 is added.
Figure 1.3 Pin Configuration (1): Bus control pins are added and NOTE 2 is added.
Tables 1.4 and 1.5 Pin Characteristics in 100-pin version (1)(2) are added.
Figure 1.4 Pin Configuration (2): Bus control pins are added and NOTE 2 is added.
3. Memory: Last 2 sentences (In memory expansion ... / Use T-V-ver.) are added.
Figure 3.1 Memory Map: NOTES 1 and 2 are added.
Table 4.1 SFR Information (1)
• Value of After Reset in PM0 is revised.
• CSR Register is added to 0008h.
• CSE Register is added to 001Bh.
• NOTES 1, 3 and 4 are added.
Table 4.16 SFR Information (16)
• Value of After Reset in PUR1 is revised.
• NOTE 1 is added.
Figure 5.2 Reset Sequence is revised.
Table 5.1 Pin Status When RESET Pin Level is "L" is revised.
Description
Summary
is revised from "L
OL OL
C-2
= –200µA" to "L = 200µA".
OL