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M16C/6N Group (M16C/6NK, M16C/6NM)
• Example of Receive Timing when Transfer Data is 8-bit Long (parity disabled, one stop bit)
UiBRG count
source
"1"
RE bit in
UiC1 register
"0"
RXDi
Transfer clock
"1"
RI bit in
UiC1 register
"0"
"H"
RTSi
"L"
"1"
IR bit in
SiRIC register
"0"
i = 0 to 2
The above timing diagram applies to the case where the register bits are set as follows:
PRYE bit in UiMR register = 0 (parity disabled)
STPS bit in UiMR register = 0 (1 stop bit)
CRD bit in UiC0 register = 0 (CTSi/RTSi enabled) and CRS bit = 1 (RTSi selected)
Figure 15.18 Receive Operation
15.1.2.1 Bit Rates
In UART mode, the frequency set by the UiBRG register (i = 0 to 2) divided by 16 become the bit rates.
Table 15.9 lists example of bit rates and settings.
Table 15.9 Example of Bit Rates and Settings
Bit-rate
Count Source
(bps)
of BRG
1200
f8
2400
f8
4800
f8
9600
f1
14400
f1
19200
f1
28800
f1
31250
f1
38400
f1
51200
f1
NOTE:
1. 24 MHz is available Normal-ver. only.
Rev.2.00
Nov 28, 2005
REJ09B0124-0200
Start bit
Sampled "L"
Reception triggered when transfer clock
is generated by falling edge of start bit
Set to "0" by an interrupt request acknowledgement or by program
Peripheral Function Clock: 16MHz Peripheral Function Clock: 20MHz Peripheral Function Clock: 24MHz
Set Value of Actual Time Set Value of Actual Time Set Value of Actual Time
BRG: n
(bps)
103 (67h)
1202
51 (33h)
2404
25 (19h)
4808
103 (67h)
9615
68 (44h)
14493
51 (33h)
19231
34 (22h)
28571
31 (1Fh)
31250
25 (19h)
38462
19 (13h)
50000
page 171 of 378
D1
D7
D0
Receive data taken in
Transferred from UARTi receive
register to UiRB register
BRG: n
(bps)
129 (81h)
1202
64 (40h)
2404
32 (20h)
4735
129 (81h)
9615
86 (56h)
14368
64 (40h)
19231
42 (2Ah)
29070
39 (27h)
31250
32 (20h)
37879
23 (17h)
52083
15. Serial Interface
Stop bit
(1)
BRG: n
(bps)
155 (9Bh)
1202
77 (4Dh)
2404
38 (26h)
4808
155 (9Bh)
9615
103 (67h)
14423
77 (4Dh)
19231
51 (33h)
28846
47 (2Fh)
31250
38 (26h)
38462
28 (1Ch)
51724
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