Renesas M16C/6NK Hardware Manual page 174

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M16C/6N Group (M16C/6NK, M16C/6NM)
UART Transmit/Receive Control Register 2
b7 b6 b5 b4 b3 b2
NOTE:
1. When using multiple transfer clock output pins, make sure the following conditions are met:
The CKDIR bit in the U1MR register = 0 (internal clock)
UARTi Special Mode Register (i = 0 to 2)
b7 b6 b5 b4 b3 b2
0
NOTES:
1. The BBS bit is set to "0" by writing "0" in a program. (Writing "1" has no effect.).
2. Underflow signal of timer A3 in UART0, underflow signal of timer A4 in UART1, underflow signal of timer
A0 in UART2.
3. When a transfer begins, the SSS bit is set to "0" (not synchronized to RXDi).
Figure 15.8 UCON Register and U0SMR to U2SMR Registers
Rev.2.00 Nov 28, 2005
REJ09B0124-0200
b1 b0
Symbol
UCON
Bit
Bit Name
Symbol
UART0 Transmit Interrupt
U0IRS
Cause Select Bit
UART1 Transmit Interrupt
U1IRS
Cause Select Bit
UART0 Continuous
U0RRM
Receive Mode Enable Bit
UART1 Continuous
U1RRM
Receive Mode Enable Bit
UART1 CLK/CLKS
CLKMD0
Select Bit 0
UART1 CLK/CLKS
CLKMD1
Select Bit 1
Separate UART0
RCSP
CTS/RTS Bit
-
Nothing is assigned. When write, set to "0".
(b7)
When read, its content is indeterminate.
b1 b0
Symbol
U0SMR to U2SMR
Bit
Bit Name
Symbol
2
IICM I C Mode Select Bit
Arbitration Lost Detecting
ABC
Flag Control Bit
Bus Busy Flag
BBS
-
Reserved Bit
(b3)
Bus Collision Detect
ABSCS
Sampling Clock Select Bit
Auto Clear Function
ACSE Select Bit of Transmit
Enable Bit
Transmit Start Condition
SSS
Select Bit
-
Nothing is assigned. When write, set to "0".
(b7)
When read, its content is indeterminate.
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Address
03B0h
Function
0 : Transmit buffer empty (Tl bit = 1)
1 : Transmission completed (TXEPT bit = 1)
0 : Transmit buffer empty (Tl bit = 1)
1 : Transmission completed (TXEPT bit = 1)
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
Effective when the CLKMD1 bit = 1
0 : Clock output from CLK1
1 : Clock output from CLKS1
0 : CLK output is only CLK1
1 : Transfer clock output from multiple
(1)
pins function selected
0 : CTS/RTS shared pin
1 : CTS/RTS separated
(CTS0 supplied from the P6_4 pin)
Address
01EFh, 01F3h, 01F7h
Function
2
0 : Other than I
2
1 : I C mode
0 : Update per bit
1 : Update per byte
0 : STOP condition detected
1 : START condition detected (busy)
Set to "0"
0 : Rising edge of transfer clock
1 : Underflow signal of timer Aj
0 : No auto clear function
1 : Auto clear at occurrence of bus
collision
0 : Not synchronized to RXDi
1 : Synchronized to RXDi
15. Serial Interface
After Reset
X0000000b
RW
RW
RW
RW
RW
RW
RW
RW
-
After Reset
X0000000b
RW
C mode
RW
RW
RW
RW
RW
(2)
RW
RW
(3)
-
(1)