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M16C/6N Group (M16C/6NK, M16C/6NM)
fCAN
CPU read signal
Updating period of
CAN module
CPU reset signal
CiSTR register
b8: State_Reset bit
0: CAN operation
mode
1: CAN reset/initial-
ization mode
i = 0, 1
Figure 23.5 When Updating Period of CAN Module Matches Access Period from CPU
CPU read signal
Updating period of
the CAN module
CPU reset signal
CiSTR register
b8: Reset state flag
0: CAN operation
mode
1: CAN reset/initial-
ization mode
i = 0, 1
Figure 23.6 With a Wait Time of 3fCAN Before CPU Read
CPU read signal
Updating period of
the CAN module
CPU reset signal
CiSTR register
b8: State_Reset bit
0: CAN operation
mode
1: CAN reset/initial-
ization mode
i = 0, 1
Figure 23.7 When Polling Period of CPU is 3fCAN or Longer
Rev.2.00
Nov 28, 2005
REJ09B0124-0200
✕
✕: When the CAN module's State_Reset bit updating period matches the CPU's read
period, it does not enter reset mode, for the CPU read has the higher priority.
Wait time
: Updated without fail in period of 3fCAN
4f
CAN
✕
✕: When the CAN module's State_Reset bit updating period matches the CPU's read
period, it does not enter reset mode, for the CPU read has the higher priority.
: Updated without fail in period of 4fCAN
page 363 of 378
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23. Usage Precaution
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