Renesas M16C/6NK Hardware Manual page 272

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M16C/6N Group (M16C/6NK, M16C/6NM)
Port Pi Direction Register (i = 0 to 7, 9 to 13)
b7 b6 b5 b4 b3 b2
NOTES:
1. Make sure the PD7 and PD9 registers are written to by the next instruction after setting the PRC2 bit in the
PRCR register to "1" (write enabled).
2. During memory expansion and microprocessor modes, the PD register for the pins functioning as bus control
pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK)
cannot be modified.
* Not available memory expansion and microprocessor modes in T/V-ver..
3. When using the ports P11 to P13, set the PU37 bit in the PUR3 register to "1" (usable).
4. The PD11 to PD13 registers are only in the 128-pin version.
Port P8 Direction Register
b7 b6 b5 b4 b3 b2
Figure20.7 PD0 to PD13 Registers
Rev.2.00 Nov 28, 2005
REJ09B0124-0200
Symbol
PD0 to PD3
b1 b0
PD4 to PD7
PD9 to PD12
(4)
PD13
Bit Symbol
PDi_0 Port Pi_0 Direction Bit
PDi_1 Port Pi_1 Direction Bit
PDi_2 Port Pi_2 Direction Bit
PDi_3 Port Pi_3 Direction Bit
PDi_4 Port Pi_4 Direction Bit
PDi_5 Port Pi_5 Direction Bit
PDi_6 Port Pi_6 Direction Bit
PDi_7 Port Pi_7 Direction Bit
b1 b0
Symbol
PD8
Bit Symbol
PD8_0 Port P8_0 Direction Bit
PD8_1 Port P8_1 Direction Bit
PD8_2 Port P8_2 Direction Bit
PD8_3 Port P8_3 Direction Bit
PD8_4 Port P8_4 Direction Bit
-
Nothing is assigned. When write, set to "0".
(b5)
When read, its content is indeterminate.
PD8_6
Port P8_6 Direction Bit
PD8_7 Port P8_7 Direction Bit
page 254 of 378
(1) (2) (3)
Address
03E2h, 03E3h, 03E6h, 03E7h
03EAh, 03EBh, 03EEh, 03EFh
(4)
03F3h, 03F6h, 03F7h, 03FAh
03FBh
Bit Name
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
Address
03F2h
Bit Name
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
20. Programmable I/O Ports
After Reset
00h
00h
00h
00h
Function RW
RW
RW
RW
RW
RW
RW
RW
RW
After Reset
00X00000b
Function RW
RW
RW
RW
RW
RW
-
RW
RW