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M16C/6N Group (M16C/6NK, M16C/6NM)
15.1.3 Special Mode 1 (I
2
I
C mode is provided for use as a simplified I
2
of the I
C mode. Figure 15.23 shows the block diagram for I
2
in the I
C mode and the register values set. Table 15.12 lists the functions in I
shows the transfer to the UiRB register and interrupt timing.
As shown in Table 15.12, the microcomputer is placed in I
"010b" and the IICM bit to "1". Because SDAi transmit output has a delay circuit attached, SDAi output
does not change state until SCLi goes low and remains stably low.
2
Table 15.10 I
C Mode Specifications
Item
Transfer Data Format
Transfer Clock
Transmission Start Condition Before transmission can start, the following requirements must be met
Reception Start Condition
Interrupt Request
Generation Timing
Error Detection
Select Function
i = 0 to 2
NOTES:
1. When an external clock is selected, the conditions must be met while the external clock is in the high state.
2. If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit in the SiRIC
register does not change.
Rev.2.00
Nov 28, 2005
REJ09B0124-0200
2
C Mode)
2
C interface compatible mode. Table 15.10 lists the specifications
Transfer data length: 8 bits
• During master
The CKDIR bit in the UiMR register = 0 (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of the UiBRG register 00h to FFh
• During slave
The CKDIR bit = 1 (external clock) : Input from SCLi pin
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
Before reception can start, the following requirements must be met
• The RE bit in the UiC1 register = 1 (reception enabled)
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
When start or stop condition is detected, acknowledge undetected, and acknowledge
detected
(2)
Overrun error
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 8th bit of the next data
• Arbitration lost
Timing at which the ABT bit in the UiRB register is updated can be selected
• SDAi digital delay
No digital delay or a delay of 2 to 8 UiBRG count source clock cycles selectable
• Clock phase setting
With or without clock delay selectable
page 175 of 378
2
C mode. Table 15.11 lists the registers used
2
C mode. Figure 15.24
2
C mode by setting the SMD2 to SMD0 bits to
Specification
15. Serial Interface
(1)
(1)
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