Renesas M16C/6NK Hardware Manual page 141

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M16C/6N Group (M16C/6NK, M16C/6NM)
Timer Ai Mode Register (i = 2 to 4)
(When using two-phase pulse signal processing)
b6 b5 b4 b3 b2
0 1 0 0
NOTES:
1. The TCK1 bit is valid for the TA3MR register. No matter how this bit is set, timers A2 and A4 always operate in normal
processing mode and x4 processing mode, respectively.
2. If two-phase pulse signal processing is desired, following register settings are required:
Set the TAiP bit in the UDF register to "1" (two-phase pulse signal processing function enabled).
Set the TAiTGH and TAiTGL bits in the TRGSR register to "00b" (TAiIN pin input).
Set the port direction bits for TAiIN and TAiOUT to "0" (input mode).
Figure 13.9 TA2MR to TA4MR Registers in Event Counter Mode (when using two-phase pulse
signal processing with timer A2, A3 or A4)
Rev.2.00 Nov 28, 2005
REJ09B0124-0200
b1 b0
Symbol
0 1
TA2MR to TA4MR
Bit Symbol
TMOD0
Operation Mode Select Bit 0 1 : Event counter mode
TMOD1
MR0
To use two-phase pulse signal processing, set this bit to "0".
MR1
To use two-phase pulse signal processing, set this bit to "1"
MR2
To use two-phase pulse signal processing, set this bit to "0".
MR3
Count Operation Type
TCK0
Select Bit
Two-Phase Pulse Signal
TCK1 Processing Operation
Select Bit
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Address After Reset
0398h to 039Ah
Bit Name
b1 b0
0 : Reload type
1 : Free-run type
0 : Normal processing operation
1 : Multiply-by-4 processing operation
(1) (2)
00h
Function
.
13. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW