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M16C/6N Group (M16C/6NK, M16C/6NM)
RXDi
RXD data
reverse circuit
STPS
1SP
0
SP
SP
1
2SP
0
STPS
2SP
1
SP
SP
0
1SP
i = 0 to 2
SP: Stop bit
PAR: Parity bit
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in UiMR register
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in UiC0 register
UiERE: Bit in UiC1 register
Figure 15.4 UARTi Transmit/Receive Unit
Rev.2.00
Nov 28, 2005
REJ09B0124-0200
IOPOL
No reverse
0
1
Reverse
PRYE
Clock
synchronous
PAR
type
disabled
0
0
PAR
1
1
PAR
UART
enabled
SMD2 to SMD0
0
0
0
0
0
PRYE
SMD2 to SMD0
PAR
enabled
UART
1
1
PAR
0
0
Clock
PAR
synchronous
disabled
type
page 152 of 378
Clock
synchronous type
UART
(7 bits)
UART
(8 bits)
UART(7 bits)
0
0
1
1
Clock
UART
synchronous type
(9 bits)
UART
(8 bits)
UART
(9 bits)
0
D8
D7 D6 D5
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
D8
D7 D6 D5
UART
(8 bits)
UART
(9 bits)
UART
Clock
synchronous type
(9 bits)
1
1
0
0
UART
UART(7 bits)
(7 bits)
Error signal output
UART
disable
(8 bits)
0
Clock
synchronous type
Error signal
output circuit
1
UiERE
Error signal output
enable
15. Serial Interface
UARTi receive register
D4 D3
D2 D1 D0
UiRB register
D4 D3 D2
D1 D0
UiTB register
UARTi transmit register
IOPOL
No reverse
TXDi
0
TXD data
reverse circuit
1
Reverse
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