Renesas M16C/6NK Hardware Manual page 73

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M16C/6N Group (M16C/6NK, M16C/6NM)
(1) Separate bus, 3-wait setting
BCLK
Write signal
Read signal
Data bus
Address bus
CS
(2)Multiplexed bus, 1- or 2-wait setting
BCLK
Write signal
Read signal
ALE
Address bus
Address bus/
Data bus Address
(3)Multiplexed bus, 3-wait setting
BCLK
Write signal
Read signal
ALE
Address bus
Address bus/
Data bus
NOTE:
1. These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and
write cycles in succession.
Figure 7.8 Typical Bus Timings Using Software Wait (2)
Rev.2.00 Nov 28, 2005
REJ09B0124-0200
Bus cycle
Output
Address
(1)
Bus cycle
Address
Data output
CS
Bus cycle
Address
Data output
Address
CS
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(1)
Bus cycle
Address
Address
(1)
Address
(1)
Bus cycle
Input
Address
(1)
Input
(1)
Bus cycle
Address
Input
7. Bus