Renesas M16C/6NK Hardware Manual page 72

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M16C/6N Group (M16C/6NK, M16C/6NM)
(1) Separate bus, No wait setting
(2) Separate bus, 1-wait setting
(3) Separate bus, 2-wait setting
NOTE:
1. These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and
write cycles in succession.
Figure 7.7 Typical Bus Timings Using Software Wait (1)
Rev.2.00 Nov 28, 2005
REJ09B0124-0200
Bus cycle
BCLK
Write signal
Read signal
Data bus
Address bus
Address
CS
Bus cycle
BCLK
Write signal
Read signal
Data bus
Address bus Address
CS
BCLK
Write signal
Read signal
Data bus
Address bus
CS
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(1)
(1)
Bus cycle
Output Input
Address
(1)
Bus cycle
Output
Address
(1)
Bus cycle
Output
Address
(1)
Input
(1)
Bus cycle
Input
Address
7. Bus