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M16C/6N Group (M16C/6NK, M16C/6NM)
(1) Transmission
Transfer clock
"1"
TE bit in
U2C1 register
"0"
"1"
TI bit in
U2C1 register
"0"
TXD2
Parity error signal sent
back from receiving end
(1)
RXD2 pin level
"1"
TXEPT bit in
U2C0 register
"0"
"1"
IR bit in
S2TIC register
"0"
The above timing diagram applies to the case where data is
transferred in the direct format.
STPS bit in U2MR register = 0 (1 stop bit)
PRY bit in U2MR register = 1 (even parity)
UFORM bit in U2C0 register = 0 (LSB first)
U2LCH bit in U2C1 register = 0 (no reverse)
U2IRS bit in U2C1 register = 1 (transmit is completed)
NOTE:
1. Because TXD2 and RXD2 are connected, a composite waveform, consisting of the TXD2 output and the parity error signal sent back
from receiving end, is generated.
(2) Reception
Transfer clock
"1"
RE bit in
U2C1 register
"0"
Transmit waveform
from transmitting end
TXD2
(1)
RXD2 pin level
RI bit in
"1"
U2C0 register
"0"
IR bit in
"1"
S2RIC register
"0"
The above timing diagram applies to the case where data is
received in the direct format.
STPS bit in U2MR register = 0 (1 stop bit)
PRY bit in U2MR register = 1 (even parity)
UFORM bit in U2C0 register = 0 (LSB first)
U2LCH bit in U2C1 register = 0 (no reverse)
U2IRS bit in U2C1 register = 1 (transmit is completed)
NOTE:
1. Because TXD2 and RXD2 are connected, a composite waveform, consisting of transmit waveform from the transmitting end and
parity error signal from receiving end, is generated.
Figure 15.32 Transmit and Receive Timing in SIM Mode
Rev.2.00
Nov 28, 2005
REJ09B0124-0200
TC
Start
bit
ST
D0 D1 D2 D3 D4 D5 D6 D7
ST
D0 D1 D2 D3 D4 D5 D6 D7
The IR bit is set to "1" at the
falling edge of transfer clock
TC
Start
bit
ST
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
ST
page 193 of 378
Write data to U2TB register
Transferred from U2TB register to UART2 transmit register
Parity
Stop
bit
bit
P
SP
ST
D0 D1 D2 D3 D4 D5 D6 D7
An "L" level returns due to the
occurrence of a parity error.
P
SP
ST
D0 D1 D2 D3 D4 D5 D6 D7
The level is detected by the
interrupt routine.
Set to "0" by an interrupt request acknowledgement or a program
TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
Parity
Stop
bit
bit
ST
D0 D1 D2 D3 D4 D5 D6 D7
P
SP
An "L" level is output from TXD2 due to
the occurrence of a parity error
D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST
Read the U2RB register
Set to "0" by an interrupt request acknowledgement or a program
TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
15. Serial Interface
P
SP
P
SP
The level is
detected by the
interrupt routine.
SP
P
P
SP
Read the U2RB register
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