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M16C/6N Group (M16C/6NK, M16C/6NM)
Main clock, PLL clock, or on-chip oscillator clock
(UART2)
RXD2
Clock source selection
CLK1 to CLK0
f1SIO or f2SIO
f8SIO
f32SIO
CLK2
CTS/RTS selected
CTS2 /
RTS2
n2: Values set to the U2BRG register
PCLK1: Bit in PCLKR register
SMD2 to SMD0, CKDIR: Bits in U2MR register
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U2C0 register
Figure 15.3 UART2 Block Diagram
Rev.2.00
Nov 28, 2005
REJ09B0124-0200
RXD polarity reversing
circuit
1/16
CKDIR
00
Internal
U2BRG
01
register
0
10
1 / (n2+1)
1/16
1
External
1/2
Clock synchronous type
(when external clock is selected)
Clock synchronous type
CKPOL
(when internal clock is selected)
CLK
polarity
reversing
circuit
CTS/RTS disabled
1
VSS
CTS/RTS disabled
CRS
0
1
0
CRD
page 151 of 378
PCLK1
f2SIO
0
1/2
1/2
f1SIO or f2SIO
f1SIO
1
1/8
f8SIO
1/4
f32SIO
UART reception
SMD2 to SMD0
010, 100, 101, 110
Reception
Clock synchronous
control circuit
type
001
UART transmission
010, 100, 101, 110
Transmission
control circuit
Clock synchronous
type
001
Clock synchronous type
(when internal clock is selected)
0
1
CKDIR
RTS2
CTS2
15. Serial Interface
TXD2
TXD
polarity
reversing
Transmit/
(1)
circuit
receive
Receive
unit
clock
Transmit
clock
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