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M16C/6N Group (M16C/6NK, M16C/6NM)
13.2 Timer B
Figure 13.15 shows a block diagram of the timer B. Figures 13.16 and 13.17 show the timer B-related
registers.
Timer B supports the following three modes. Use the TMOD1 and TMOD0 bits in the TBiMR register (i = 0
to 5) to select the desired mode.
• Timer mode
• Event counter mode
• Pulse period/pulse width measuring mode : The timer measures pulse period or pulse width of an
Select clock source
TCK1 to TCK0
00
f1 or f2
01
f8
10
f32
11
fC32
TBj overflow
(1)
Polarity Switching
TBiIN
and Edge Pulse
TCK1 to TCK0, TMOD1 to TMOD0: Bits in TBiMR register
TBiS: Bit in TABSR register or TBSR register
i = 0 to 5
j = i - 1 except j = 2 when i = 0, j = 5 when i = 3
NOTE:
1. Overflow or underflow
Figure 13.15 Timer B Block Diagram
Rev.2.00
Nov 28, 2005
REJ09B0124-0200
00: Timer
10:
Pulse period measurement mode,
pulse width measurement mode
TCK1
1
01: Event counter
0
Counter Reset Circuit
page 130 of 378
: The timer counts an internal count source.
: The timer counts pulses from an external device or over
flows or underflows of other timers.
external signal.
TMOD1 to TMOD0
TBiS
TBi
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
Timer B5
High-order Bits of Data Bus
Low-order Bits of Data Bus
Low-order
High-order
8 bits
8 bits
Reload Register
Counter
Addresses
TBj
0391h - 0390h
Timer B2
0393h - 0392h
Timer B0
0395h- 0394h
Timer B1
01D1h- 01D0h
Timer B5
01D3h- 01D2h
Timer B3
01D5h- 01D4h
Timer B4
13. Timers
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