Renesas M16C/6NK Hardware Manual page 181

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M16C/6N Group (M16C/6NK, M16C/6NM)
15.1.1.1 Counter Measure for Communication Error Occurs
If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode,
follow the procedures below.
• Resetting the UiRB register (i = 0 to 2)
(1) Set the RE bit in the UiC1 register to "0" (reception disabled)
(2) Set the SMD2 to SMD0 bits in the UiMR register to "000b" (serial interface disabled)
(3) Set the SMD2 to SMD0 bits in the UiMR register to "001b" (clock synchronous serial I/O mode)
(4) Set the RE bit in the UiC1 register to "1" (reception enabled)
• Resetting the UiTB register (i = 0 to 2)
(1) Set the SMD2 to SMD0 bits in the UiMR register to "000b" (serial interface disabled)
(2) Set the SMD2 to SMD0 bits in the UiMR register to "001b" (clock synchronous serial I/O mode)
(3) "1" (transmission enabled) is written to the TE bit in the UiC1 register, regardless of the TE bit
15.1.1.2 CLK Polarity Select Function
Use the CKPOL bit in the UiC0 register (i = 0 to 2) to select the transfer clock polarity. Figure 15.12
shows the polarity of the transfer clock.
(1) When the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling
edge and the receive data taken in at the rising edge of the transfer clock)
CLKi
TXDi
RXDi
(2) When the CKPOL bit in the UiC0 register = 1 (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock)
CLKi
TXDi
RXDi
i = 0 to 2
* This applies to the case where the UFORM bit in the UiC0 register = 0
(LSB first) and the UiLCH bit in the UiC1 register = 0 (no reverse).
NOTES:
1. When not transferring, the CLKi pin outputs a high signal.
2. When not transferring, the CLKi pin outputs a low signal.
Figure 15.12 Transfer Clock Polarity
Rev.2.00 Nov 28, 2005
REJ09B0124-0200
D0 D1 D2
D0 D1 D2
D0 D1 D2
D0 D1 D2
page 163 of 378
D3 D4 D5 D6
D3 D4 D5 D6
D3 D4 D5 D6
D3 D4 D5 D6
15. Serial Interface
(NOTE 1)
D7
D7
(NOTE 2)
D7
D7