Renesas M16C/6NK Hardware Manual page 93

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M16C/6N Group (M16C/6NK, M16C/6NM)
Figure 8.12 shows the state transition from normal operation mode to stop mode and wait mode. Figure
8.13 shows the state transition in normal operation mode.
Table 8.8 shows a state transition matrix describing allowed transition and setting. The vertical line shows
current state and horizontal line show state after transition.
All oscillators stopped
Stop Mode
CM07 = 0
CM06 = 1
CM05 = 0
CM11 = 0
Stop Mode
(3)
CM10 = 1
Stop Mode
Stop Mode
CM05, CM06, CM07: Bits in CM0 register
CM10, CM11: Bits in CM1 register
NOTES:
Do not go directly from PLL operation mode to wait or stop mode.
1.
2.PLL operation mode can be entered from high-speed mode. Similarly, PLL operation mode can be changed back to high-speed mode.
3.Write to the CM0 and CM1 registers per 16 bits with the CM21 bit in the CM2 register = 0 (on-chip oscillator stops).
Since the operation starts from the main clock after exiting stop mode, the time until the CPU operates can be reduced.
4.The on-chip oscillator clock divided by 8 provides the CPU clock.
5.Before entering stop mode, be sure to set the CM20 bit in the CM2 register to "0" (oscillation stop, re-oscillation detection function disabled).
Figure 8.12 State Transition to Stop Mode and Wait Mode
Rev.2.00 Nov 28, 2005
REJ09B0124-0200
(5)
CM10 = 1
Interrupt
Interrupt
(5)
CM10 = 1
When
low
power
dissipation
mode
CM10 = 1 (5)
Interrupt
(5)
CM10 = 1
Interrupt (4)
page 75 of 378
Reset
Medium-Speed Mode
(divided-by-8 mode)
High-Speed Mode,
Medium-Speed Mode
(NOTES 1, 2)
When
low-
speed
PLL Operation Mode
mode
Low-Speed Mode,
Low Power Dissipation Mode
On-chip Oscillator Mode,
On-chip Oscillator Dissipation Mode
Normal Mode
8. Clock Generating Circuit
CPU operation stopped
WAIT
instruction
Wait Mode
Interrupt
WAIT
instruction
Wait Mode
Interrupt
WAIT
instruction
Wait Mode
Interrupt
WAIT
instruction
Wait Mode
Interrupt