Renesas M16C/6NK Hardware Manual page 176

Under development
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M16C/6N Group (M16C/6NK, M16C/6NM)
UARTi Special Mode Register 4 (i = 0 to 2)
b7 b6 b5 b4 b3 b2
NOTE:
1. Set to "0" when each condition is generated.
Figure 15.10 U0SMR4 to U2SMR4 Registers
Rev.2.00 Nov 28, 2005
REJ09B0124-0200
b1 b0
Symbol
U0SMR4 to U2SMR4
Bit
Bit Name
Symbol
Start Condition
STAREQ
Generate Bit
Restart Condition
RSTAREQ
Generate Bit
Stop Condition
STPREQ
Generate Bit
SCL,SDA Output
STSPSEL
Select Bit
ACKD ACK Data Bit
ACK Data Output
ACKC
Enable Bit
SCL Output Stop
SCLHI
Enable Bit
SWC9 SCL Wait Bit 3
page 158 of 378
Address
01ECh, 01F0h, 01F4h
Function
0 : Clear
(1)
1 : Start
0 : Clear
(1)
1 : Start
0 : Clear
(1)
1 : Start
0 : Start and stop conditions not output
1 : Start and stop conditions output
0 : ACK
1 : NACK
0 : Serial interface data output
1 : ACK data output
0 : Disabled
1 : Enabled
0 : SCL "L" hold disabled
1 : SCL "L" hold enabled
15. Serial Interface
After Reset
00h
RW
RW
RW
RW
RW
RW
RW
RW
RW