Software Commands - Renesas M16C/6NK Hardware Manual

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M16C/6N Group (M16C/6NK, M16C/6NM)

21.3.5 Software Commands

Software commands are described below. The command code and data must be read and written in 16-bit
unit, to and from even addresses in the user ROM area. When writing command code, the high-order 8
bits (D15 to D8) are ignored.
Table 21.4 lists the software commands.
Table 21.4 Software Commands
Software Command
Read Array
Read Status Register
Clear Status Register
Program
Block Erase
Erase All Unlocked Block
Lock Bit Program
Read Lock Bit Status
SRD:data in SRD register (D7 to D0)
WA: Address to be written (The address specified in the first bus cycle is the same even address as the
address specified in the second bus cycle.)
WD: 16-bit write data
BA: Highest-order block address (must be an even address)
✕:
Any even address in the user ROM area
xx: High-order 8 bits of command code (ignored)
NOTE
1. It is only blocks 0 to 12 that can be erased by the erase all unlocked block command.
Block A cannot be erased. The block erase command must be used to erase the block A.
21.3.5.1 Read Array Command (FFh)
The read array command reads the flash memory.
By writing command code "xxFFh" in the first bus cycle, read array mode is entered. Content of a
specified address can be read in 16-bit unit after the next bus cycle.
The microcomputer remains in read array mode until another command is written. Therefore, contents
from multiple addresses can be read consecutively.
21.3.5.2 Read Status Register Command (70h)
The read status register command reads the status register (refer to 21.3.7 Status Register (SRD
Register) for detail).
By writing command code "xx70h" in the first bus cycle, the status register can be read in the second bus
cycle. Read an even address in the user ROM area.
Do not execute this command in EW1 mode.
21.3.5.3 Clear Status Register Command (50h)
The clear status register command clears the status register.
By writing "xx50h" in the first bus cycle, the FMR07, FMR06 bits in the FMR0 register are set to "00b"
and the SR5, SR4 bits in the status register are set to "00b".
Rev.2.00 Nov 28, 2005
REJ09B0124-0200
Mode
Write
Write
Write
Write
Write
(1)
Write
Write
Write
page 273 of 378
First Bus Cycle
Data
Address
(D15 to D0)
✕
xxFFh
✕
xx70h
✕
xx50h
xx40h
WA
✕
xx20h
✕
xxA7h
xx77h
BA
✕
xx71h
21. Flash Memory Version
Second Bus Cycle
Data
Mode Address
(D15 to D0)
- -
✕
Read SRD
-
-
Write WD
WA
Write xxD0h
BA
✕
Write xxD0h
Write xxD0h
BA
Write xxD0h
BA
-
-