Renesas M16C/6NK Hardware Manual page 208

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M16C/6N Group (M16C/6NK, M16C/6NM)
(1) ABSCS Bit in UiSMR Register (bus collision detect sampling clock select)
Transfer clock
TXDi
RXDi
Timer Aj
(2) ACSE Bit in UiSMR Register (auto clear of transmit enable bit)
Transfer clock
TXDi
RXDi
IR bit in
UiBCNIC register
TE bit in
UiC1 register
(3) SSS Bit in UiSMR Register (transmit start condition select)
If SSS bit = 0, the serial I/O starts sending data one transfer clock cycle after the transmission enable condition is met.
Transfer clock
TXDi
Transmission enable condition is met
If SSS bit = 1, the serial I/O starts sending data at the rising edge
CLKi
TXDi
RXDi
NOTES:
1.The falling edge of RXDi when IOPOL bit = 0; the rising edge of RXDi when IOPOL bit = 1.
2.The transmit condition must be met before the falling edge
i = 0 to 2
This diagram applies to the case where IOPOL bit =1 (reversed)
Figure 15.31 Bus Collision Detect Function-Related Bits
Rev.2.00 Nov 28, 2005
REJ09B0124-0200
If ABSCS bit = 0, bus collision is determined at the rising edge of the transfer clock
ST D0 D1
Input to TAjIN
Timer Aj: timer A3 when UART0; timer A4 when UART1; timer A0 when UART2
ST D0 D1
ST D0
ST D0
(NOTE 2)
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D2 D3 D4 D5
If ABSCS bit = 1, bus collision is determined when timer
Aj (one-shot timer mode) underflows.
D2 D3 D4 D5
D1 D2 D3 D4 D5
(1)
of RXDi
D1 D2 D3 D4 D5
of RXDi.
(1)
15. Serial Interface
D6 D7 D8 SP
D6 D7 D8 SP
If the ACSE bit = 1 (automatically
clear when bus collision occurs),
the TE bit is set to "0"
(transmission disabled) when
the IR bit in the UiBCNIC register = 1
(unmatching detected).
D6 D7 D8 SP
D6 D7 D8 SP