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M16C/6N Group (M16C/6NK, M16C/6NM)
Table 8.8 Allowed Transition and Setting
High-Speed Mode,
Medium-Speed Mode
Low-Speed
(2)
Mode
Low Power
Dissipation Mode
PLL Operation
(2)
Mode
On-chip Oscillator
Mode
On-chip Oscillator Low
Power Dissipation Mode
Stop Mode
Wait Mode
-: Cannot transit
NOTES:
1. Avoid making a transition when the CM20 bit = 1 (oscillation stop, re-
oscillation detection function enabled). Set the CM20 bit to "0" (oscillation
stop, re-oscillation detection function disabled) before transiting.
2. On-chip oscillator clock oscillates and stops in low-speed mode. In this
mode, the on-chip oscillator can be used as peripheral function clock. Sub
clock oscillates and stops in PLL operation mode. In this mode, sub clock
can be used as peripheral function clock.
3. PLL operation mode can only be entered from and changed to high-speed
mode.
4. Set the CM06 bit to "1" (divide-by-8 mode) before transiting from on-chip
oscillator mode to high- or medium-speed mode.
5. When exiting stop mode, the CM06 bit is set to "1" (divide-by-8 mode).
6. If the CM05 bit is set to "1" (main clock stop), then the CM06 bit is set to "1"
(divide-by-8 mode).
7. A transition can be made only when sub clock is oscillating.
8. State transitions within the same mode (divide-by-n values changed or sub
clock oscillation turned on or off) are shown in the table below.
Sub Clock Oscillating
No Divide- Divide- Divide- Divide- No Divide- Divide- Divide- Divide-
Division by-2 by-4 by-8 by-16 Division by-2 by-4 by-8 by-16
No Division
(4)
Divide-by-2 (3)
Divide-by-4 (3)
(4)
Divide-by-8 (3)
(4)
Divide-by-16 (3)
(4)
No Division (2)
-
Divide-by-2
-
(2)
Divide-by-4
-
-
Divide-by-8
-
-
Divide-by-16
-
-
9. ( ):setting method. See right table.
Rev.2.00
Nov 28, 2005
REJ09B0124-0200
(9)
High-Speed Mode, Low-Speed Low Power PLL Operation On-chip Oscillator On-chip Oscillator
Medium-Speed
(2)
Mode
Dissipation Mode Mode (2)
Mode
(7)
(NOTE 8)
(9)
(8)
-
(10)
(3)
(12)
-
(4)
(14)
-
-
-
(5)
(18)
(18)
(18)
(18)
Sub Clock Turned Off
(5)
(7)
(6)
(1)
(5)
(7)
(6)
-
(7)
(6)
-
(5)
(6)
-
(5)
(7)
-
-
-
-
-
-
-
(3)
(2)
-
-
(3)
-
(2)
-
(3)
-
-
(2)
(3)
page 77 of 378
State after transition
Mode
(3)
-
(13)
(15)
(1) (6)
(11)
-
-
-
-
-
-
-
-
(NOTE 8)
-
-
(10)
(18)
-
(18)
(18)
-
(18)
(1) CM04=0
(2) CM04=1
( 3) CM06=0
( 4) CM06=0
( 5) CM06=0
( 6) CM06=0
(7) CM06=1
(8) CM07=0
(9) CM07=1
(10) CM05=0
(11) CM05=1
-
-
-
-
(12) PLC07=0
(1)
-
-
-
( 13) PLC07=1
-
(1)
-
-
-
-
(1)
-
(14) CM21=0
-
-
-
(1)
( 15) CM21=1
(4)
(5)
(7)
(6)
(5)
(7)
(6)
(16) CM10=1
(4)
(7)
(6)
(17) WAIT
(4)
(5)
(6)
(18) Hardware
(4)
(5)
(7)
CM04, CM05, CM06, CM07: Bits in CM0 register
CM10, CM11, CM16, CM17: Bits in CM1 register
CM20, CM21
PLC07
8. Clock Generating Circuit
Stop
Low Power
Mode
Dissipation Mode
(1)
-
(16)
(1)
-
(16)
(1)
-
(16)
-
-
(1)
(1)
(11)
(16)
(1)
(NOTE 8)
(16)
(5)
(5)
(18)
(18)
-
Setting
Operation
Sub clock turned off
Sub clock oscillating
CPU clock no division
CM17=0
mode
CM16=0
CPU clock divide-by-2
CM17=0
mode
CM16=1
CPU clock divide-by-4
CM17=1
mode
CM16=0
CPU clock divide-by-16
CM17=1
mode
CM16=1
CPU clock divide-by-8 mode
Main clock, PLL clock
or on-chip oscillator
clock selected
Sub clock selected
Main clock oscillating
Main clock turned off
Main clock selected
CM11=0
PLL clock selected
CM11=1
Main clock or
PLL clock selected
On-chip oscillator clock
selected
Transition to stop mode
Transition to wait mode
instruction
Exit stop mode or wait
interrupt
mode
: Bits in CM2 register
: Bit in PLC0 register
Wait
Mode
(17)
(17)
(17)
-
(17)
(17)
-
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