Renesas M16C/6NK Hardware Manual page 105

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M16C/6N Group (M16C/6NK, M16C/6NM)
Interrupt Control Register
b7 b6 b5 b4 b3 b2
0
NOTES:
1. To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that
register. For details, refer to 23.8 Interrupt.
2. When the BYTE pin is low and the processor mode is memory expansion or microprocessor mode, set the
ILVL2 to ILVL0 bits in the INT5IC to INT3IC registers to "000b" (interrupt disabled).
* Not available memory expansion and microprocessor modes in T/V-ver..
3. This bit can only be reset by writing "0" (Do not write "1").
4. If the IFSR10 to IFSR15 bits in the IFSR1 register and the IFSR23 to IFSR25 bits in the IFSR2 register are
"1" (both edges), set the POL bit in the INT0IC to INT8IC register to "0" (falling edge). INT6IC to INT8IC registers
are in the 128-pin version.
5. Set the POL bit in the S3IC register to "0" (falling edge) when the IFSR00 bit in the IFSR0 register = 1 and the
IFSR16 bit in the IFSR1 register = 0 (SI/O3 selected).
6. Set the POL bit in the S4IC register to "0" (falling edge) when the IFSR03 bit in the IFSR0 register = 1 and the
IFSR17 bit in the IFSR1 register = 0 (SI/O4 selected).
7. Use the IFSR03 bit in the IFSR0 register and the IFSR17 bit in the IFSR1 register to select.
8. Use the IFSR00 bit in the IFSR0 register and the IFSR16 bit in the IFSR1 register to select.
9. Use the IFSR20 bit in the IFSR2 register to select.
The INT7IC register is only in the 128-pin version. In the 100-pin version, set the IFSR20 bit to "0" (Timer A2).
10. Use the IFSR21 bit in the IFSR2 register to select.
The INT6IC register is only in the 128-pin version. In the 100-pin version, set the IFSR21 bit to "0" (Timer A3).
11. Use the IFSR22 bit in the IFSR2 register to select.
The INT8IC register is only in the 128-pin version. In the 100-pin version, set the IFSR22 bit to "0" (Timer B1).
Figure 10.4 Interrupt Control Registers (2)
Rev.2.00 Nov 28, 2005
REJ09B0124-0200
(1)
Symbol
(2)
INT3IC
C1RECIC/S4IC/INT5IC
C1TRMIC/S3IC/INT4IC
INT0IC to INT2IC
b1 b0
TA2IC/INT7IC
TA3IC/INT6IC
TB1IC/INT8IC
Bit Symbol
ILVL0
Interrupt Priority Level
ILVL1
Select Bit
ILVL2
Interrupt Request Bit
IR
Polarity Select Bit
POL
-
Reserved Bit
(b5)
Nothing is assigned. When write, set to "0".
-
(b7-b6)
When read, their contents are indeterminate.
page 87 of 378
Address
0044h
(2) (7)
0048h
(2) (8)
0049h
005Dh to 005Fh
(9)
0057h
(10)
0058h
(11)
005Bh
Bit Name
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : Interrupt not requested
1 : Interrupt requested
0 : Selects falling edge
1 : Selects rising edge
Set to "0"
10. Interrupt
After Reset
XX00X000b
XX00X000b
XX00X000b
XX00X000b
XX00X000b
XX00X000b
XX00X000b
Function
RW
RW
RW
RW
RW
(4) (5) (6)
RW
RW
-
(3)