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M16C/6N Group (M16C/6NK, M16C/6NM)
SDAi
Noise
Filter
SCLi
Noise
Filter
This diagram applies to the case where the SMD2 to SMD0 bits in the UiMR register = 010b and the IICM bit in the UiSMR register = 1.
i = 0 to 2
IICM: Bit in UiSMR register
IICM2, SWC, ALS, SWC2, SDHI: Bits in UiSMR2 register
STSPSEL, ACKD, ACKC: Bits in UiSMR4 register
NOTE:
1. If the IICM bit =1, the pins can be read even when the PD6_2, PD6_6 or PD7_1 bit = 1 (output mode).
2
Figure 15.23 I
C Mode Block Diagram
Rev.2.00
Nov 28, 2005
REJ09B0124-0200
STSPSEL=1
Delay
circuit
STSPSEL=0
ACKC=1
ACKC=0
SDHI
ALS
ACKD bit
D
Arbitration
Q
T
Start condition
detection
Stop condition
detection
Falling edge
detection
Port register
IICM=0
R
I/O port
Q
Internal clock
STSPSEL=0
UARTi
IICM=1
STSPSEL=1
External
clock
page 176 of 378
Start and stop condition generation block
SDA(STSP)
SCL(STSP)
IICM2=1
Transmission
register
UARTi
Reception register
UARTi
S
Bus
Q
R
busy
D
Q
T
D
Q
ACK
T
(1)
9th bit
SWC2
CLK
control
UARTi
9th bit falling edge
R
S
SWC
15. Serial Interface
DMA0, DMA1 request
(UART1: DMA0 only)
UARTi transmit,
NACK interrupt
request
IICM=1 and
IICM2=0
DMA0
(UART0, UART2)
IICM2=1
UARTi receive,
ACK interrupt request,
DMA1 request
IICM=1 and
IICM2=0
NACK
Start/stop condition
detection
interrupt request
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