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REVISION HISTORY
Rev.
Date
Page
2.00 Nov. 28, 2005
37
38
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43, 44
45 to 55 7. Bus is added.
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63
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73
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M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual
5.2 Software Reset, 5.3 Watchdog Timer Reset, 5.4 Oscillation Stop Detection Reset:
Last sentence (Processor mode remains ...) is added to each section.
5.5 Internal Space is added.
6.1 Types Processor Mode is added.
Table 6.1 Features of Processor Modes is added.
6.2 Setting Processor Modes is added.
Table 6.2 Processor Mode After Hardware Reset and Table 6.3 PM01 to PM00 Bits Set
Values and Processor Modes are added.
Figure 6.1 PM0 Register is revised.
Figure 6.2 PM1 Register is revised.
Figures 6.4 to 6.7 Memory Map and CS Area in Memory Expansion Mode and Microprocessor
Mode (1) to (4) are added.
Table 8.1 Clock Generating Circuit Specifications: NOTE 1 is added.
Figure 8.8 PLC0 Register: NOTE 4 is added.
Figure 8.9 Examples of Main Clock Connection Circuit is revised.
Figure 8.10 Examples of Sub Clock Connection Circuit is revised.
8.1.4 PLL Clock
• 9th line: The sentence (When the PLL ... to) is added.
• NOTE 1 is added.
Table 8.2 Example for Setting PLL Clock Frequencies: NOTES 2 and 3 are added.
8.2.1 CPU Clock and BCLK
• 10th line: The sentence (During memory expansion ...) is added.
8.4.1.2 PLL Operation Mode: NOTE 1 is added.
8.4.1.6 On-chip Oscillator Mode: Last sentence (When the operation mode is ...) is added.
8.1.1.7 On-chip Oscillator Low Power Dissipation Mode: Last sentence (When the
operation mode is ...) is deleted.
Table 8.4 Pin Status During Wait Mode is revised.
Table 8.6 Interrrupts to Stop Mode and Use Conditions is added.
Table 8.7 Pin Status in Stop Mode is revised.
Figure 8.13 State Transition in Normal Operation Mode: NOTE 7 is deleted.
Figure 10.4 Interrupt Control Registers (2): NOTE 2 is added.
10.5.8 Returning from an Interrupt Routine: Last sentence (Register bank ...) is added.
10.5.9 Interrupt Priority: First sentence (If two or more...) is revised.
10.5.10 Interrupt Priority Resolution Circuit: First sentence (The interrupt priority level ...)
is revised.
Figure 10.12 IFSR1 Register: NOTES 2 and 4 are revised.
10.10 Address Match Interrupt
• Second line from the bottom: The sentence (Note that when ...) is added.
Table 12.1 DMAC Specifications: DMA transfer Cycles is added.
12.1 Transfer Cycle: 3rd and 4th sentences (During ... / Furthermore ...) are revised
and NOTES 1 and 2 are added.
12.1.2 Effect of BYTE Pin Level is added.
Description
Summary
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C-3
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