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M16C/6N Group (M16C/6NK, M16C/6NM)
13. Timers
Eleven 16-bit timers, each capable of operating independently of the others, can be classified by function as
either timer A (five) and timer B (six). The count source for each timer acts as a clock, to control such timer
operations as counting, reloading, etc.
Figures 13.1 and 13.2 show block diagrams of Timer A and Timer B configuration, respectively.
Main clock
PLL clock
On-chip
oscillator clock
f1 or f2 f8 f32 fC32
TA0IN
TA1IN
TA2IN
TA3IN
TA4IN
PCLK0: Bit in PCLKR register
TCK1 to TCK0, TMOD1 to TMOD0: Bits in TAiMR register (i = 0 to 4)
TAiTGH to TAiTGL: Bits in ONSF register or TRGSR register
NOTE:
1. Be aware that TA0IN shares the pin with RXD2, SCL2 and TB5IN.
Figure 13.1 Timer A Configuration
Rev.2.00
Nov 28, 2005
REJ09B0124-0200
PCLK0 = 0
f2
1/2
f1
PCLK0 = 1
1/8
1/4
TCK1 to TCK0
00
TMOD1 to TMOD0 00:
01
10
10
11
01
Noise
filter
00
11
TA0TGH to TA0TGL
TCK1 to TCK0
00
TMOD1 to TMOD0 00:
01
10
10
11
01
Noise
filter
00
11 TA1TGH t0 TA1TGL
TCK1 to TCK0
00
TMOD1 to TMOD0 00:
01
10
10
11
01
Noise
filter
00
11 TA2TGH to TA2TGL
TCK1 to TCK0
00
TMOD1 to TMOD0 00:
01
10
10
11
01
Noise
filter
00
11 TA3TGH to TA3TGL
TCK1 to TCK0
00
TMOD1 to TMOD0 00:
01
10
11
10
01
Noise
filter
00
11 TA4TGH to TA4TGL
Timer B2 overflow or underflow
page 113 of 378
f1 or f2
XCIN
f8
Set the CPSR bit in the
CPSRF register to "1"
f32
(prescaler reset)
Timer mode
10 :
One-shot timer mode
Pulse width measuring mode
11 :
Timer A0
Event counter mode
01:
Timer mode
10 :
One-shot timer mode
Pulse width measuring mode
11 :
Timer A1
Event counter mode
01:
Timer mode
One-shot timer mode
10 :
Pulse width measuring mode
11 :
Timer A2
Event counter mode
01:
Timer mode
One-shot timer mode
10 :
11 :
Pulse width measuring mode
Timer A3
Event counter mode
01:
Timer mode
One-shot timer mode
10 :
Pulse width measuring mode
11 :
Timer A4
Event counter mode
01:
13. Timers
Clock prescaler
1/32
fC32
Reset
Timer A0 interrupt
Timer A1 interrupt
Timer A2 interrupt
Timer A3 interrupt
Timer A4 interrupt
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