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M16C/6N Group (M16C/6NK, M16C/6NM)
Priority level of each interrupt
INT1
Timer B2
Timer B0, SI/O6
Timer A3, INT6
Timer A1
UART1 Reception, ACK1
UART0 Reception, ACK0
UART2 Reception, ACK2
INT2
INT0
Timer B1, INT8
Timer A4
Timer A2, INT7
Timer A0
UART1 Transmission, NACK1
UART0 Transmission, NACK0
A/D Conversion, Key Input
DMA1
UART2 Bus Collision Detection
CAN1 Successful Reception, SI/O4, INT5
Timer B4, UART1 Bus Collision Detection
INT3
CAN0 Successful Reception
UART2 Transmission, NACK2
CAN0/1 Error (, Key Input)
DMA0
CAN1 Successful Transmission, SI/O3, INT4
Timer B3, UART0 Bus Collision Detection
Timer B5, SI/O5
CAN0 Successful Transmission
CAN0/1 Wake-up
IPL
I Flag
Address Match
Oscillation Stop and Re-oscillation Detection
Watchdog Timer
DBC
NMI
NOTES:
1. If the PCLK6 bit in the PCLKR register is set to "1", the priority level of key input interrupt can be changed.
2. The SI/O5, SI/O6 and INT6 to INT8 registers are only in the 128-pin version.
Figure 10.10 Interrupts Priority Select Circuit
Rev.2.00
Nov 28, 2005
REJ09B0124-0200
Level 0
(initial value)
(2)
(2)
(2)
(2)
(1)
(1)
(2)
page 93 of 378
Highest
Priority of peripheral function interrupts
(if priority levels are same)
Lowest
Interrupt request level resolution output to clock generating circuit
(Figure 8.1 Clock Generating Circuit)
Interrupt request accepted
10. Interrupt
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