Table of Contents
Advertisement
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
2
Table 15.12 I
C Mode Functions
Serial I/O Mode
Function
(SMD2 to SMD0 =
001b, IICM = 0)
Factor of Interrupt
-
Number 6, 7 and
(1) (5) (7)
10
Factor of Interrupt
UARTi transmission
Number 15, 17 and
Transmission started
(1) (6)
19
or completed
(selected by UiIRS)
Factor of Interrupt
UARTi reception
Number 16, 18 and
When 8th bit received
(1) (6)
20
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Timing for Transferring
CKPOL = 0 (rising edge)
Data from UART
CKPOL = 1 (falling edge)
Reception Shift Register
to UiRB Register
UARTi Transmission
Not delayed
Output Delay
Functions of P6_3,
TXDi output
P6_7 and P7_0 Pins
Functions of P6_2,
RXDi input
P6_6 and P7_1 Pins
Functions of P6_1,
CLKi input or
P6_5 and P7_2 Pins
output selected
Noise Filter Width
15 ns
Read RXDi and
Possible when the
SCLi Pins Levels
corresponding port
direction bit = 0
Initial Value of TXDi
CKPOL = 0 (H)
and SDAi Outputs
CKPOL = 1 (L)
Initial and End
-
Value of SCLi
(6)
DMA1 Factor
UARTi reception
Store Received
1st to 8th bits of the received data are stored into bit
Data
7 to bit 0 in the UiRB register
Read Received
The UiRB register status is read
Data
i = 0 to 2
NOTES:
1. If the source or cause of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt may
inadvertently be set to "1" (interrupt requested). (Refer to 23.8 Interrupts.)
If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to set
the IR bit to "0" (interrupt not requested) after changing those bits.
• SMD2 to SMD0 bits in UiMR register
• IICM2 bit in UiSMR2 register
2. Set the initial value of SDAi output while the SMD2 to SMD0 bits in the UiMR register = 000b (serial interface disabled).
3. Second data transfer to the UiRB register (rising edge of SCLi 9th bit)
4. First data transfer to the UiRB register (falling edge of SCLi 9th bit)
5. See Figure 15.26 STSPSEL Bit Functions.
6. See Figure 15.24 Transfer to UiRB Register and Interrupt Timing.
7. When using UART0, be sure to set the IFSR06 bit in the IFSR0 register to "1" (cause of interrupt: UART0 bus collision detection).
When using UART1, be sure to set the IFSR07 bit in the IFSR0 register to "1" (cause of interrupt: UART1 bus collision detection).
Rev.2.00
Nov 28, 2005
REJ09B0124-0200
Clock
Synchronous
(NACK/ACK interrupt)
CKPH = 0
(No clock delay)
Start condition detection or stop condition detection
(See Table 15.13 STSPSEL Bit Functions)
No acknowledgment detection
(NACK)
Rising edge of SCLi 9th bit
Acknowledgment detection (ACK)
Rising edge of SCLi 9th bit
Rising edge of SCLi 9th bit
Delayed
SDAi input/output
SCLi input/output
- (Cannot be used in I
200 ns
Always possible no matter how the corresponding port direction bit is set
The value set in the port register before setting I
H
Acknowledgment detection (ACK)
• IICM bit in UiSMR register
• CKPH bit in UiSMR3 register
page 178 of 378
2
I
C Mode (SMD2 to SMD0 = 010b, IICM = 1)
IICM2 = 0
(UART transmit/receive interrupt)
CKPH = 1
(Clock delay)
(No clock delay)
UARTi transmission
Rising edge of
SCLi 9th bit
UARTi reception
Falling edge of SCLi 9th bit
Falling edge of
SCLi 9th bit
2
C mode)
L
H
UARTi reception
Falling edge of SCLi 9th bit
1st to 7th bits of the received data are stored into
bit 6 to bit 0 in the UiRB
register, 8th bit is stored into
bit 8 in the UiRB register
15. Serial Interface
IICM2 = 1
CKPH = 0
CKPH = 1
(Clock delay)
UARTi transmission
Falling edge of
SCLi next to the
9th bit
Falling and rising
edges of SCLi 9th
bit
2
(2)
C mode
L
1st to 8th bits are
stored into bit 7 to bit
0 in UiRB register
Bit 6 to bit 0 in the UiRB
(4)
register
are read as bit
7 to bit 1. Bit 8 in the UiRB
register is read as bit 0.
(3)
Advertisement
Table of Contents
