Renesas M16C/6NK Hardware Manual page 188

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M16C/6N Group (M16C/6NK, M16C/6NM)
(1) Example of Transmit Timing when Transfer Data is 8-bit Long (parity enabled, one stop bit)
Transfer clock
"1"
TE bit in
UiC1 register
"0"
"1"
TI bit in
UiC1 register
"0"
"H"
CTSi
"L"
TXDi
"1"
TXEPT bit in
UiC0 register
"0"
"1"
IR bit in
SiTIC register
"0"
The above timing diagram applies to the case where the register bits are set
as follows:
PRYE bit in UiMR register = 1 (parity enabled)
STPS bit in UiMR register = 0 (1 stop bit)
CRD bit in UiC0 register = 0 (CTS/RTS enabled), and CRS bit = 0 (CTS selected)
UilRS bit = 1 (an interrupt request occurs when transmit completed):
U0IRS bit is bit 0 in UCON register
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
(2) Example of Transmit Timing when Transfer Data is 9-bit Long (parity disabled, two stop bits)
Transfer clock
"1"
TE bit in
UiC1 register
"0"
"1"
TI bit in
UiC1 register
"0"
TXDi
"1"
TXEPT bit in
UiC0 register
"0"
"1"
IR bit in
SiTIC register
"0"
The above timing diagram applies to the case where the register bits are set
as follows:
PRYE bit in UiMR register = 0 (parity disabled)
STPS bit in UiMR register = 1 (2 stop bits)
CRD bit in UiC0 register = 1 (CTS/RTS disabled)
UilRS bit = 0 (an interrupt request occurs when transmit buffer becomes empty):
U0IRS bit is bit 0 in UCON register
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
Figure 15.17 Transmit Operation
Rev.2.00 Nov 28, 2005
REJ09B0124-0200
The transfer clock stops momentarily as CTS
The transfer clock starts as the transfer starts immediately CTSi changes to "L".
TC
Write data to the UiTB register
Start
bit
ST D0 D1 D2 D3 D4 D5 D6 D7
TC
Write data to the UiTB register
Start
bit
ST D 0 D1 D2 D3 D4 D5 D6 D7
Set to "0" by an interrupt request acknowledgement or by program
page 170 of 378
is "H" when the stop bit is checked.
i
Transferred from UiTB register to UARTi transmit register
Parity Stop
bi t bi t
P SP ST D0 D1 D2 D3 D4 D5 D6 D7
Set to "0" by an interrupt request acknowledgement or by program
TC = 16 (n + 1) / fj or 16 (n + 1) / f E XT
fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of UiBRG count source (external clock)
n : value set to UiBRG
i = 0 to 2
Transferred from UiTB register to UARTi
transmit register
Stop Stop
bi t bi t
D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT: frequency of UiBRG count source (external clock)
n : value set to UiBRG
i = 0 to 2
15. Serial Interface
Stopped pulsing
because the TE bit
= 0
ST
D0 D1
P SP
ST
D8 SPSP D0 D1