Event Counter Mode - Renesas M16C/6NK Hardware Manual

Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)

13.2.2 Event Counter Mode

In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers. Table 13.7 lists specifications in event counter mode. Figure 13.19 shows TBiMR register in
event counter mode.
Table 13.7 Specifications in Event Counter Mode
Item
Count Source
Count Operation
Divide Ratio
Count Start Condition
Count Stop Condition
Interrupt Request Generation Timing Timer underflow
TBiIN Pin Function
Read from Timer
Write to Timer
i = 0 to 5
j = i - 1, except j = 2 if i = 0, j = 5 if i = 3
NOTE:
1. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register, and the TB3S to TB5S
bits are assigned to the bit 5 to bit 7 in the TBSR register.
Timer Bi Mode Register (i= 0 to 5)
b7 b6 b5 b4
NOTES:
1. Effective when the TCK1 bit = 0 (input from TBiIN pin). If the TCK1 bit = 1 (TBj overflow or underflow), these bits can
be set to "0" or "1".
2. The port direction bit for the TBiIN pin must be set to "0" (input mode).
Figure 13.19 TB0MR to TB5MR Registers in Event Counter Mode
Rev.2.00 Nov 28, 2005
REJ09B0124-0200
• External signals input to TBiIN pin (effective edge can be selected in program)
• Timer Bj overflow or underflow
• Down-count
• When the timer underflows, it reloads the reload register contents and
continues counting
1/(n+1) n: set value of the TBi register
(1)
Set TBiS bit to "1" (start counting)
Set TBiS bit to "0" (stop counting)
Count source input
Count value can be read by reading the TBi register
• When not counting and until the 1st count source is input after counting start
Value written to the TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to the TBi register is written to only reload register
(Transferred to counter when reloaded next)
b3 b2 b1 b0
Symbol
0 1
TB0MR to TB2MR
TB3MR to TB5MR
Bit Symbol
TMOD0
Operation Mode Select Bit 0 1 : Event counter mode
TMOD1
MR0
Count Polarity Select
(1)
Bit
MR1
TB0MR, TB3MR registers
Set to "0" in event counter mode
MR2 TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
When write in event counter mode, set to "0".
MR3
When read in event counter mode, its content is indeterminate.
Has no effect in event counter mode.
TCK0
Can be set to "0" or "1".
Event Clock Select Bit
TCK1
page 134 of 378
Specification
Address After Reset
039Bh to 039Dh 00XX0000b
00XX0000b
01DBh to 01DDh
Bit Name Function
b1 b0
b3 b2
0 0 : Counts falling edge of external signal
0 1 : Counts rising edge of external signal
1 0 : Counts falling and rising edges of
external signal
1 1 : Do not set a value
0 : Input from TBiIN pin
1 : TBj overflow or underflow
(j = i — 1, except j = 2 if i = 0,
0000h to FFFFh
RW
RW
RW
RW
RW
RW
-
RO
RW
(2)
RW
j = 5 if i = 3)
13. Timers