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M16C/6N Group (M16C/6NK, M16C/6NM)
Count source
Measurement pulse
Reload register
transfer timing
Timing at which counter
reaches "0000h"
TBiS bit
IR bit in
TBiIC register
MR3 bit in
TBiMR register
The TB0S to TB2S bits are assigned to bit 5 to bit 7 in the TABSR register, and the TB3S to TB5S bits
are assigned to bit 5 to bit 7 in the TBSR register.
i = 0 to 5
NOTES:
1. Counter is initialized at completion of measurement.
2. Timer has overflown.
3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are "00b" (measure the interval
from falling edge to falling edge of the measurement pulse).
Figure 13.21 Operation Timing When Measuring Pulse Period
Count source
Measurement pulse
Reload register
transfer timing
Timing at which counter
reaches "0000h"
TBiS bit
IR bit in
TBiIC register
MR3 bit in
TBiMR register
The TB0S to TB2S bits are assigned to bit 5 to bit 7 in the TABSR register, and the TB3S to TB5S bits
are assigned to bit 5 to bit 7 in the TBSR register.
i = 0 to 5
NOTES:
1. Counter is initialized at completion of measurement.
2. Timer has overflown.
3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are "10b" (measure the
interval from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge
of the measurement pulse).
Figure 13.22 Operation Timing When Measuring Pulse Width
Rev.2.00
Nov 28, 2005
REJ09B0124-0200
"H"
"L"
counter
"1"
"0"
"1"
"0"
Set to "0" upon accepting an interrupt request or by writing in program
"1"
"0"
"H"
"L"
counter
"1"
"0"
"1"
"0"
Set to "0" upon accepting an interrupt request or by
writing in program
"1"
"0"
page 137 of 378
Transfer
(indeterminate value)
(NOTE 1)
Transfer
Transfer
Transfer
(indeterminate
(measured value)
(measured
value)
value)
(NOTE 1)
(NOTE 1)
(NOTE 1)
Transfer
(measured value)
(NOTE 1)
(NOTE 2)
Transfer
(measured value)
(NOTE 1)
(NOTE 2)
13. Timers
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