Renesas M16C/6NK Hardware Manual page 233

16-bit single-chip microcomputer m16c family / m16c/60 series
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M16C/6N Group (M16C/6NK, M16C/6NM)
A/D Control Register 0
b7
b6
b5
b4
b3
b2
1 1
NOTE:
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D Control Register 1
b7
b6
b5
b4
b3
b2
1
1
NOTES:
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. AN0_0 to AN_7, and AN2_0 to AN2_7 can be used in same way as AN0 to AN7. Use the ADGSEL1 to ADGSEL0
bits in the ADCON2 register to select the desired pin.
3. If the VCUT bit is reset from "0" (VREF unconnected) to "1" (VREF connected), wait for 1 µs or more before
starting A/D conversion.
Figure 16.8 ADCON0 Register and ADCON1 Register in Repeat Sweep Mode 1
Rev.2.00
Nov 28, 2005
REJ09B0124-0200
(1)
b1
b0
Symbol
ADCON0
Bit Symbol
CH0
Analog Input Pin Select Bit
CH1
CH2
MD0
A/D Operation Mode
Select Bit 0
MD1
Trigger Select Bit
TRG
A/D Conversion Start Flag
ADST
Frequency Select Bit 0
CKS0
(1)
b1
b0
Symbol
ADCON1
Bit Symbol
SCAN0
A/D Sweep Pin Select Bit
SCAN1
A/D Operation Mode
MD2
Select Bit 1
BITS
8/10-Bit Mode Select Bit
Frequency Select Bit 1
CKS1
VCUT
VREF Connect Bit
OPA0
External Op-Amp
Connection Mode Bit
OPA1
page 215 of 378
Address
After Reset
03D6h
00000XXXb
Bit Name
Invalid in repeat sweep mode 1
b4 b3
1 1 : Repeat sweep mode 0 or
Repeat sweep mode 1
0 : Software trigger
1 : ADTRG trigger
0 : A/D conversion disabled
1 : A/D conversion started
Refer to NOTE 2 for ADCON2
Register
Address
After Reset
03D7h
00h
Bit Name
When repeat sweep mode 1 is selected
b1 b0
0 0 : AN0 (1 pin)
0 1 : AN0, AN1 (2 pins)
1 0 : AN0 to AN2 (3 pins)
1 1 : AN0 to AN3 (4 pins)
Set to "1" when repeat sweep
mode 1 is selected
0 : 8-bit mode
1 : 10-bit mode
Refer to NOTE 2 for ADCON2
Register
(3)
1 : VREF connected
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : Do not set a value
1 0 : Do not set a value
1 1 : External op-amp connection mode
16. A/D Converter
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW
Function
RW
RW
RW
(2)
RW
RW
RW
RW
RW
RW

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