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M16C/6N Group (M16C/6NK, M16C/6NM)
Table 15.11 Registers to Be Used and Settings in I
Register
Bit
(1)
UiTB
0 to 7
UiRB
(1)
0 to 7
8
ABT
OER
UiBRG
0 to 7
UiMR
(1)
SMD2 to SMD0
CKDIR
IOPOL
UiC0
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
UiC1
TE
TI
RE
RI
U2IRS
(2)
U2RRM
(2)
UiLCH, UiERE
UiSMR
IICM
ABC
BBS
3 to 7
UiSMR2
IICM2
CSC
SWC
ALS
STAC
SWC2
SDHI
7
UiSMR3
0, 2, 4 and NODC
CKPH
DL2 to DL0
UiSMR4
STAREQ
RSTAREQ
STPREQ
STSPSEL
ACKD
ACKC
SCLHI
SWC9
IFSR0
IFSR06, ISFR07
UCON
U0IRS, U1IRS
2 to 7
i = 0 to 2
NOTES:
1. Not all register bits are described above. Set those bits to "0" when writing to the registers in I
2. Set the bit 4 and bit 5 in the U0C1 and U1C1 registers to "0". The U0IRS, U1IRS, U0RRM and U1RRM bits are in the UCON
register.
Rev.2.00
Nov 28, 2005
REJ09B0124-0200
Set transmission data
Reception data can be read
ACK or NACK is set in this bit
Arbitration lost detection flag
Overrun error flag
Set a transfer rate
Set to "010b"
Set to "0"
Set to "0"
Select the count source for the UiBRG register
Invalid because the CRD bit = 1
Transmit register empty flag
Set to "1"
Set to "1"
Set to "0"
Set to "1"
Set this bit to "1" to enable transmission
Transmit buffer empty flag
Set this bit to "1" to enable reception
Reception complete flag
Invalid
,
Set to "0"
Set to "1"
Select the timing at which arbitration-lost
is detected
Bus busy flag
Set to "0"
See Table 15.12 I
Set this bit to "1" to enable clock synchronization
Set this bit to "1" to have SCLi output fixed to "L" at the falling edge of the 9th bit of clock
Set this bit to "1" to have SDAi output
stopped when arbitration-lost is detected
Set to "0"
Set this bit to "1" to have SCLi output forcibly pulled low
Set this bit to "1" to disable SDAi output
Set to "0"
Set to "0"
See Table 15.12 I
Set the amount of SDAi digital delay
Set this bit to "1" to generate start condition
Set this bit to "1" to generate restart condition
Set this bit to "1" to generate stop condition
Set this bit to "1" to output each condition
Select ACK or NACK
Set this bit to "1" to output ACK data
Set this bit to "1" to have SCLi output
stopped when stop condition is detected
Set to "0"
Set to "1"
Invalid
Set to "0"
page 177 of 378
2
C Mode
Function
Master
Invalid
Invalid
Set to "1"
Invalid
Invalid
2
C Mode Functions
Set to "0"
Set to "0"
Set this bit to "1" to initialize UARTi at
start condition detection
2
C Mode Functions
Set to "0"
Set to "0"
Set to "0"
Set to "0"
Set to "0"
Set this bit to "1" to set the SCLi to "L" hold
at the falling edge of the 9th bit of clock
15. Serial Interface
Slave
2
C mode.
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