Renesas M16C/6NK Hardware Manual page 80

Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
CAN0/1 Clock Select Register
b7 b6 b5 b4 b3
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (Write enabled).
2. Set only when the Reset bit in the CiCTLR register (i = 0, 1) = 1 (Reset/Initialization mode).
3. Before setting this bit to "1", set the Sleep bit in the CiCTLR register to "1" (Sleep mode enabled).
Figure 8.6 CCLKR Register
Processor Mode Register 2
b7 b6 b5 b4 b3
0 0
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).
2. The PM20 bit become effective when the PLC07 bit in the PLC0 register is set to "1" (PLL on). Change the PM20
bit when the PLC07 bit is set to "0" (PLL off). Set the PM20 bit t "0" (2 waits) when PLL clock > 16MHz.
3. Once this bit is set to "1", it cannot be set to "0" in a program.
4. Setting the PM22 bit to "1" results in the following conditions:
The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer count source.
The CM10 bit in the CM1 register is disabled against write. (Writing a "1" has no effect, nor is stop mode entered.)
The watchdog timer does not stop when in wait mode or hold state.
Figure 8.7 PM2 Register
Rev.2.00 Nov 28, 2005
REJ09B0124-0200
(1)
b2 b1 b0
Symbol
CCLKR
Bit Symbol
CCLK0
CCLK1 CAN0 Clock Select Bits
CCLK2
CAN0 CPU Interface
CCLK3
Sleep Bit
CCLK4
CCLK5 CAN1 Clock Select Bits
CCLK6
CAN1 CPU Interface
CCLK7
Sleep Bit
(1)
b2 b1 b0 Symbol
0
PM2
Bit Symbol
Specifying Wait when
Accessing SFR at PLL
PM20
Operation
-
Reserved Bit
(b1)
WDT Count Source
PM22
Protective Bit
-
Reserved Bit
(b4-b3)
- Nothing is assigned. When write, set to "0".
(b7-b5)
When read, their contents are indeterminate.
page 62 of 378
Address After Reset
025Fh 00h
Bit Name
b2 b1 b0
0 0 0 No division
0 0 1 : Divide-by-2
0 1 0 : Divide-by-4
0 1 1 : Divide-by-8
(2)
1 0 0: Divide-by-16
1 0 1 :
1 1 0 :
1 1 1 :
0: CAN0 CPU interface operating
(3)
1: CAN0 CPU interface in sleep
b6 b5 b4
0 0 0 No division
0 0 1 : Divide-by-2
0 1 0 : Divide-by-4
0 1 1 : Divide-by-8
(2)
1 0 0: Divide-by-16
1 0 1 :
1 1 0 :
1 1 1 :
0: CAN1 CPU interface operating
(3)
1: CAN1 CPU interface in sleep
Address After Reset
001Eh XXX00000b
Bit Name
0 : 2 waits
1 : 1 wait
(2)
Set to "0"
0 : CPU clock is used for the
watchdog timer count source
1 : On-chip oscillator clock is used for
(3) (4)
the watchdog timer count source
Set to "0"
8. Clock Generating Circuit
Function
RW
RW
RW
Do not set a value
RW
RW
RW
RW
Do not set a value
RW
RW
Function
RW
RW
RW
RW
RW
-