Renesas M16C/6NK Hardware Manual page 197

Under development
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M16C/6N Group (M16C/6NK, M16C/6NM)
(1) IICM2 = 0 (ACK and NACK interrupts), CKPH = 0 (no clock delay)
1st bit
SCLi
D7
SDAi
(2) IICM2 = 0, CKPH = 1 (clock delay)
1st bit
SCLi
D7
SDAi
(3) IICM2 = 1 (UART transmit/receive interrupt), CKPH = 0
1st bit
SCLi
D7
SDAi
(4) IICM2 = 1, CKPH = 1
1st bit
SCLi
D7
SDAi
i = 0 to 2
This diagram applies to the case where the following condition is met.
The CKDIR bit in the UiMR register = 0 (slave selected)
Figure 15.24 Transfer to UiRB Register and Interrupt Timing
Rev.2.00 Nov 28, 2005
REJ09B0124-0200
2nd bit 3rd bit 4th bit 5th bit
D6 D5 D4 D3
2nd bit 3rd bit 4th bit 5th bit
D6 D5 D4 D3
2nd bit 3rd bit 4th bit 5th bit
D6 D5 D4 D3
2nd bit 3rd bit 4th bit 5th bit
D6 D5 D4 D3
b15
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6th bit 7th bit 8th bit 9th bit
D2 D1 D0 D8 (ACK, NACK)
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to UiRB register
b15
6th bit 7th bit 8th bit 9th bit
D8 (ACK, NACK)
D2 D1 D0
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to UiRB register
b15
6th bit 7th bit 8th bit 9th bit
D2 D1 D0 D8 (ACK, NACK)
Receive interrupt
(DMA1 request)
Transfer to UiRB register
b15
6th bit 7th bit 8th bit 9th bit
D2 D1 D0 D8 (ACK, NACK)
Receive interrupt
(DMA1 request)
Transfer to UiRB register
b9 b8 b7 b0
D0 D7 D6 D5 D4 D3 D2 D1
UiRB register
15. Serial Interface
b9 b8 b7
D D D D D D D D
8 7 6 5 4 3 2 1
UiRB register
b9 b8 b7
D8 D7 D6 D5 D4 D3 D2 D1
UiRB register
Transmit interrupt
b9 b8 b7
D0 D7 D6 D5 D4 D3 D2
UiRB register
Transmit interrupt
Transfer to UiRB register
b15 b9 b8 b7
D8 D7 D6 D5 D4 D3 D2 D1
UiRB register
b0
D
0
b0
D0
b0
D1
b0
D0