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M16C/6N Group (M16C/6NK, M16C/6NM)
Table 21.5 Status Register
Bits in Status
Bits in FMR0
Register
Register
SR0 (D0)
-
SR1 (D1)
-
SR2 (D2)
-
SR3 (D3)
-
SR4 (D4)
FMR06
SR5 (D5)
FMR07
SR6 (D6)
-
SR7 (D7)
FMR00
D0 to D7: These data bus are read when the read status register command is executed.
NOTE:
1. The FMR06 bit (SR4) and FMR07 bit (SR5) are set to "0" by executing the clear status register command.
When the FMR06 bit (SR4) or FMR07 bit (SR5) is set to "1", the program, block erase, erase all
unlocked block, and lock bit program commands are not accepted.
Rev.2.00
Nov 28, 2005
REJ09B0124-0200
Status Name
Reserved
Reserved
Reserved
Reserved
Program status
Erase status
Reserved
Sequencer status
page 279 of 378
Contents
"0"
-
-
-
-
Terminated normally
Terminated in error
Terminated normally
Terminated in error
-
Busy
21. Flash Memory Version
Value after
Reset
"1"
-
-
-
-
-
-
-
-
0
0
-
-
Ready
1
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