Renesas M16C/6NK Hardware Manual page 205

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M16C/6N Group (M16C/6NK, M16C/6NM)
15.1.4.1 Clock Phase Setting Function
One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit in
the UiSMR3 register and the CKPOL bit in the UiC0 register.
Make sure the transfer clock polarity and phase are the same for the master and salves to be communicated.
Figure 15.28 shows the transmission and reception timing in master (internal clock).
Figure 15.29 shows the transmission and reception timing (CKPH = 0) in slave (external clock).
Figure 15.30 shows the transmission and reception timing (CKPH = 1) in slave (external clock).
Clock output
(CKPOL = 0, CKPH = 0)
Clock output
(CKPOL = 1, CKPH = 0)
Clock output
(CKPOL = 0, CKPH = 1)
Clock output
(CKPOL = 1, CKPH = 1)
Data output timing
Data input timing
Figure 15.28 Transmission and Reception Timing in Master Mode (Internal Clock)
Rev.2.00 Nov 28, 2005
REJ09B0124-0200
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
D0
"L"
page 187 of 378
D1 D2 D3 D4
15. Serial Interface
D5 D6 D7