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M16C/6N Group (M16C/6NK, M16C/6NM)
fAD
Software trigger
ADTRG
VREF
0
AVSS
1
PM00
(1)
PM01
Port P0 group
AN0_0
AN0_1
AN0_2
AN0_3
AN0_4
AN0_5
AN0_6
AN0_7
Port P2 group
AN2_0
AN2_1
AN2_2
AN2_3
AN2_4
AN2_5
AN2_6
AN2_7
OPA0=1
ANEX0
OPA1=1
ANEX1
NOTE:
1. Port P0 group (AN0_0 to AN0_7) can be used as analog input pins even when PM01 to PM00 bits are set to "01b"
(memory expansion mode) and PM05 to PM04 bits are set to "11b" (multiplex bus allocated to the entire CS space).
* Not available memory expansion mode in T/V-ver..
Figure 16.1 A/D Converter Block Diagram
Rev.2.00
Nov 28, 2005
REJ09B0124-0200
A/D conversion rate selection
CKS2
0
1
1/3
TRG
0
1
VCUT
Resistor ladder
Successive conversion register
AD0 register
AD1 register
AD2 register
AD3 register
AD4 register
AD5 register
AD6 register
AD7 register
Data bus high-order
Data bus low-order
Port P10 group
AN0
AN0
AN0
CH2 to CH0
AN0
=000b
AN0
=001b
AN0
=010b
AN0
=011b
AN0
=100b
=101b
=110b
=111b
CH2 to CH0
=000b
=001b
=010b
=011b
=100b
=101b
=110b
(1)
PM01 to PM00=00b
=111b
ADGSEL1 to ADGSEL0=10b
OPA1 to OPA0=11b
PM01 to PM00=00b
ADGSEL1 to ADGSEL0=11b
OPA1 to OPA0=11b
page 203 of 378
1
1/2
1/2
0
A/D trigger
ADCON1 register
ADCON0 register
Decoder
for A/D register
ADCON2 register
for channel
CH2 to CH0
=000b
ADGSEL1 to ADGSEL0=00b
=001b
=010b
=011b
=100b
=101b
=110b
ADGSEL1 to ADGSEL0=10b
=111b
ADGSEL1 to ADGSEL0=11b
ADGSEL1 to ADGSEL0=00b
OPA1 to OPA0=11b
OPA1 to OPA0
=01b
OPA1=1
16. A/D Converter
CKS1
1
φAD
0
CKS0
VREF
Decoder
selection
Comparator
VIN
(1)
OPA1 to OPA0=00b
PM01 to PM00=00b
OPA1 to OPA0=00b
PM01 to PM00=00b
OPA1 to OPA0=00b
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