Table of Contents
Advertisement
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
CM04
CM10=1
S
Q
(stop mode)
R
S
Q
WAIT instruction
R
RESET
Software reset
NMI
Interrupt request level
judgment output
PM00, PM01
CM00, CM01, CM02, CM04, CM05, CM06, CM07 : BIts in CM0 register
CM10, CM11, CM16, CM17
PCLK0, PCLK1
CM21, CM27
CCLK0 to CCLK2, CCLK4 to CCLK6
Oscillation stop, re-oscillation detection circuit
Pulse generating circuit
for clock edge detection
Main clock
and charge,
discharge control
PLL frequency synthesizer
Main clock
Figure 8.1 Clock Generating Circuit
Rev.2.00
Nov 28, 2005
REJ09B0124-0200
Sub clock oscillation circuit
XCIN
XCOUT
CM21
On-chip
oscillator
Oscillation stop,
re-oscillation
detection circuit
XIN
XOUT
PLL frequency
synthesizer
PLL clock
Main clock
1
Main clock
CM05
0
oscillation circuit
: Bits in PM0 register
: Bits in CM1 register
: Bits in PCLKR register
: Bits in CM2 register
: Bits in CCLKR register
CM27 = 0
Charge,
discharge
circuit
CM27 = 1
Programmable
counter
Phase
comparator
page 57 of 378
I/O ports
Sub clock
On-chip oscillator
clock
a
CM21=1
CM21=0
CM11
CM02
b
1/2
1/2
a
1/2
CM06=0
CM17-CM16=01b
CM06=0
CM17-CM16=00b
Reset
generating
circuit
Oscillation stop,
re-oscillation detection
interrupt generating
circuit
Voltage
Charge
control
pump
oscillator
(VCO)
Internal
lowpass filter
8. Clock Generating Circuit
CM01-CM00=00b
PM01-PM00=00b, CM01-CM00=01b
PM01-PM00=00b, CM01-CM00=10b
PM01-PM00=00b,
CM01-CM00=11b
fC32
1/32
fCAN0
Divider
By CCLK0,1 and 2
f
CAN1
Divider
By CCLK4,5 and 6
PCLK0=1
PCLK0=0
PCLK0=1
PCLK0=0
PCLK1=1
PCLK1=0
b
c
d
CM07=0
e
Divider
CPU clock
CM07=1
c
d
1/2
1/2
1/2
1/32
1/4
1/8
1/16
CM06=0
CM17-CM16=11b
CM06=1
CM06=0
CM17-CM16=10b
e
Details of divider
Oscillation stop
detection reset
Oscillation stop,
re-oscillation detection
interrupt signal
CM21 switch signal
1/2
PLL clock
CLKOUT
f
AD
BCLK
Advertisement
Table of Contents
