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M16C/6N Group (M16C/6NK, M16C/6NM)
Table 12.1 DMAC Specifications
Item
No. of Channels
Transfer Memory Space
Maximum No. of Bytes Transferred 128 Kbytes (with 16-bit transfer) or 64 Kbytes (with 8-bit transfer)
DMA Request Factors
Channel Priority
Transfer Unit
Transfer Address Direction
Transfer Mode Single Transfer
Repeat Transfer When the DMAi transfer counter underflows, it is reloaded with the value
DMA Interrupt Request
Generation Timing
DMA Start Up
DMA Shutdown Single Transfer • When the DMAE bit is set to "0" (disabled)
Repeat Transfer When the DMAE bit is set to "0" (disabled)
Reload Timing for Forward
Address Pointer and Transfer
Counter
DMA Transfer Cycles
i = 0, 1
NOTES:
1. DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the
interrupt control register.
2. The selectable causes of DMA requests differ with each channel.
3. Make sure that no DMAC-related registers (addresses 0020h to 003Fh) are accessed by the DMAC.
Rev.2.00
Nov 28, 2005
REJ09B0124-0200
2 (cycle steal method)
• From any address in the 1-Mbyte space to a fixed address
• From a fixed address to any address in the 1-Mbyte space
• From a fixed address to a fixed address
(1) (2)
Falling edge of INT0 or INT1
Both edge of INT0 or INT1
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 transfer, UART0 reception interrupt requests
UART1 transfer, UART1 reception interrupt requests
UART2 transfer, UART2 reception interrupt requests
SI/O3, SI/O4 interrupt requests
A/D conversion interrupt requests
Software triggers
DMA0 > DMA1 (DMA0 takes precedence)
8 bits or 16 bits
forward or fixed (The source and destination addresses cannot both be
in the forward direction.)
Transfer is completed when the DMAi transfer counter underflows
after reaching the terminal count.
of the DMAi transfer counter reload register and a DMA transfer is
continued with it.
When the DMAi transfer counter underflowed
Data transfer is initiated each time a DMA request is generated when the
The DMAE bit in the DMAiCON register = 1 (enabled).
• After the DMAi transfer counter underflows
When a data transfer is started after setting the DMAE bit to "1" (enabled),
the forward address pointer is reloaded with the value of the SARi or the
DARi pointer whichever is specified to be in the forward direction and the
DMAi transfer counter is reloaded with the value of the DMAi transfer
counter reload register.
Minimum 3 cycles between SFR and internal RAM
page 104 of 378
Specification
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12. DMAC
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