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M16C/6N Group (M16C/6NK, M16C/6NM)
Memory Expansion Mode and Microprocessor Mode
(Effective for setting with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
(Common to setting with wait and setting without wait)
BCLK
HOLD input
HLDA output
P0, P1, P2,
P3, P4,
(1)
P5_0 to P5_2
NOTE:
1. The above pins are set to high-impedance regardless of the input level of the BYTE pin,
the PM06 bit in the PM0 register and the PM11 bit in the PM1 register.
Measuring conditions :
VCC = 3.3 V
Input timing voltage : Determined with V
Output timing voltage: Determined with V
Figure 22.14 Timing Diagram (2)
Rev.2.00
Nov 28, 2005
REJ09B0124-0200
tsu(RDY–BCLK)
t
t
su(HOLD–BCLK)
h(BCLK–HOLD)
t
d(BCLK–HLDA)
page 321 of 378
22. Electric Characteristics (Normal-ver.)
t
d(BCLK–HLDA)
Hi–Z
= 0.6 V, V
= 2.7 V
IL
IH
= 1.65 V, V
= 1.65 V
OL
OH
VCC = 3.3V
th(BCLK–RDY)
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