Renesas M16C/6NK Hardware Manual page 71

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M16C/6N Group (M16C/6NK, M16C/6NM)
Table 7.8 Software Wait Related Bits and Bus Cycles
PM2 Register
Area Bus Mode
PM20 Bit
SFR
-
-
Internal
-
ROM, RAM
-
External
Separate
Area
Bus
Multiplexed
(2)
Bus
NOTES:
________
1. To use the RDY signal, set this bit to "0 ".
2. To access in multiplexed bus mode, set the corresponding bit of CS0W to CS3W to "0" (with wait state).
3. After reset, the PM17 bit is set to "0" (without wait state), all of the CS0W to CS3W bits are set to "0"
(with wait state), and the CSE register is set to "00h" (one wait state for CS0 to CS3). Therefore, the
internal RAM and internal ROM are accessed with no wait state, and all external areas are accessed
with one wait state.
4. When the selected CPU clock source is the PLL clock, the number of wait cycles can be altered by the
PM20 bit in the PM2 register. When using PLL clock over 16 MHz, be sure to set the PM20 bit to "0"
(2 wait cycles).
5. When the PM17 bit is set to "1" and access an external area, set the CSiW bits (i = 0 to 3) to "0" (with
wait sate).
Rev.2.00 Nov 28, 2005
REJ09B0124-0200
CSR Register
CS3W Bit
PM1 Register
CS2W Bit
(5)
PM17 Bit
CS1W Bit
CS0W Bit
-
0
-
1
0
-
1
-
0
-
- -
- -
- -
- 1
- -
- -
- -
1
-
page 53 of 378
CSE Register
(1)
CS31W to CS30W Bits
(1)
CS21W to CS20W Bits
(1)
CS11W to CS10W Bits
(1)
CS01W to CS00W Bits
- -
- -
- -
- -
1 00b
0 00b
0 01b
0 10b
0 00b
0 00b
0 01b
0 10b
0 00b
Software
Bus Cycle
Wait
- 3 BCLK cycles
- 2 BCLK cycles
No wait 1 BCLK cycle
1 wait 2 BCLK cycles
No wait 1 BCLK cycle (read)
2 BCLK cycles (write)
1 wait 2 BCLK cycles
2 waits 3 BCLK cycles
3 waits 4 BCLK cycles
1 wait 2 BCLK cycles
1 wait 3 BCLK cycles
2 waits 3 BCLK cycles
3 waits 4 BCLK cycles
1 wait 3 BCLK cycles
_______ _______
7. Bus
(4)
(4)
(3)
(3)