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Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
1.5 Pin Configuration
Figures 1.3 and 1.4 show the pin configuration (top view). Tables 1.4 to 1.8 list the pin characteristics.
PIN CONFIGURATION (top view)
P1_2/D10
P1_1/D9
P1_0/D8
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
P10_0/AN0
P9_7/ADTRG/SIN4
P9_6/ANEX1/CTX0/SOUT4
P9_5/ANEX0/CRX0/CLK4
NOTES:
1. P7_1 and P9_1 are N channel open-drain pins.
2. Not available the bus control pins (except CLKOUT pin) in T/V-ver..
Figure 1.3 Pin Configuration (Top View) (1)
Rev.2.00
Nov 28, 2005
REJ09B0124-0200
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M16C/6N Group
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(M16C/6NK)
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AVSS
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VREF
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AVCC
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1. Overview
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P4_2/A18
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P4_3/A19
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P4_4/CS0
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P4_5/CS1
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P4_6/CS2
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P4_7/CS3
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P5_0/WRL/WR
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P5_1/WRH/BHE
P5_2/RD
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P5_3/BCLK
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P5_4/HLDA
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P5_5/HOLD
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P5_6/ALE
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P5_7/RDY/CLKOUT
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P6_0/CTS0/RTS0
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P6_1/CLK0
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P6_2/RXD0/SCL0
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P6_3/TXD0/SDA0
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P6_4/CTS1/RTS1/CTS0/CLKS1
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P6_5/CLK1
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P6_6/RXD1/SCL1
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P6_7/TXD1/SDA1
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P7_0/TXD2/SDA2/TA0OUT
(1)
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P7_1/RXD2/SCL2/TA0IN/TB5IN
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P7_2/CLK2/TA1OUT/V
Package: PLQP0100KB-A
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