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M16C/6N Group (M16C/6NK, M16C/6NM)
INV00 to INV07: Bits in INVC0 register
INV10 to INV15: Bits in INVC1 register
DUi, DUBi: Bits in IDBi register (i = 0, 1)
TA1S to TA4S: Bits in TABSR register
PWCON: Bits in TB2SC register
Reload Control Signal for Timer A1
Timer B2 Underflow
f1 or f2
Timer B2
(Timer Mode)
Write signal to
Timer B2
INV10
Start Trigger Signal for Timers A1, A2, A4
TA4 Register
TA41 Register
Reload
Trigger
Timer A4 Counter
(One-Shot Timer Mode)
INV11
T Q
When setting the TA4S bit to "0",
signal is set to "0"
TA1 Register
TA11 Register
Reload
Trigger
Timer A1 Counter
(One-Shot Timer Mode)
INV11
T Q
When setting the TA1S bit to "0",
signal is set to "0"
TA2 Register
TA21 Register
Reload
Trigger
Timer A2 Counter
(One-Shot Timer Mode)
INV11
T Q
When setting the TA2S bit to "0",
signal is set to "0"
NOTE:
1. Transfer trigger is generated only when the IDB0 and IDB1 registers are set and the first timer B2 underflows,
if the INV06 bit is set to "0" (triangular wave modulation mode).
Figure 14.1 Three-Phase Motor Control Timer Function Block Diagram
Rev.2.00
Nov 28, 2005
REJ09B0124-0200
INV13
INV01
INV11
INV00
1
0
PWCON
0
1/2
1
INV12
INV07
INV06
Transfer Trigger
Trigger
U-phase Output
Control Circuit
DU1
bit
Reload Control
Signal for Timer A4
D Q
T
Timer A4
DUB1
One-Shot
bit
Pulse
D Q
T
INV06
Trigger
Reload Control
Signal for Timer A1
Timer A1
V-Phase Output
One-Shot
Control Circuit
Pulse
INV06
Trigger
Reload Control
Signal for Timer A2
Timer A2
W-Phase Output
One-Shot
Control Circuit
Pulse
page 139 of 378
14. Three-Phase Motor Control Timer Function
ICTB2 Register n=1 to 15
Write signal to INV03 bit
Circuit to set Interrupt
Generation Frequency
Timer B2
ICTB2 Counter
Interrupt
n=1 to 15
Request Bit
Reload Register
n = 1 to 255
Trigger
Dead Time
(1)
Timer
D Q
n = 1 to 255
T
DU0
bit
U-Phase
Output Signal
D Q
T
Three-Phase
Output
DUB0
Shift Register
bit
(U Phase)
D Q
D Q
T
T
U-Phase
Output Signal
Trigger
Dead Time
Timer
n = 1 to 255
D Q
T
V-Phase
Output Signal
D Q
T
V-Phase
Output Signal
Trigger
Dead Time
Timer
n = 1 to 255
D Q
T
W-Phase
Output Signal
D Q
T
W-Phase
Output Signal
Switching to P8_0, P8_1 and P7_2 to P7_5 is not shown in this diagram.
INV03
Value to be written to
D Q
INV03 bit
T
R
RESET
NMI
INV05
INV02
INV04
INV14
Inverse
Control
Inverse
Control
Inverse
Control
Inverse
Control
Inverse
Control
Inverse
Control
U
U
V
V
W
W
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