Register Configuration; Register Descriptions; Timer Counter (Tcnt)-H'ffcc (Tmr0), H'ffd4 (Tmr1) - Hitachi H8/329 Series Hardware Manual

7.1.4 Register Configuration

Table 7-2 lists the registers of the 8-bit timer module. Each channel has an independent set of
registers.
Table 7-2. 8-Bit Timer Registers
Name
Timer control register
Timer control/status register
Timer constant register A
Timer constant register B
Timer counter
Serial/timer control register
Note: * Software can write a "0" to clear bits 7 to 5, but cannot write a "1" in these bits.

7.2 Register Descriptions

7.2.1 Timer Counter (TCNT)—H'FFCC (TMR0), H'FFD4 (TMR1)
Bit 7
Initial value 0
Read/Write R/W
Each timer counter (TCNT) is an 8-bit up-counter that increments on a pulse generated from an
internal or external clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) of the timer
control register (TCR). The CPU can always read or write the timer counter.
The timer counter can be cleared by an external reset input or by an internal compare-match signal
generated at a compare-match event. Clock clear bits 1 and 0 (CCLR1 and CCLR0) of the timer
control register select the method of clearing.
When a timer counter overflows from H'FF to H'00, the overflow flag (OVF) in the timer
control/status register (TCSR) is set to "1."
Abbreviation
TCR
TCSR
TCORA
TCORB
TCNT
STCR
6 5
0 0
R/W R/W R/W
145
R/W Initial value TMR0
R/W H'00
R/(W)* H'10
R/W H'FF
R/W H'FF
R/W H'00
R/W H'F8
4 3 2
0 0 0
R/W R/W
Address
TMR1
H'FFC8 H'FFD0
H'FFC9 H'FFD1
H'FFCA H'FFD2
H'FFCB H'FFD3
H'FFCC H'FFD4
H'FFC3 H'FFC3
1 0
0 0
R/W R/W