Section 4 Address Break; Register Descriptions - Hitachi H8/3672 Series Hardware Manual

The address break simplifies on-board program debugging. It requests an address break interrupt
when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR.
Break conditions that can be set include instruction execution at a specific address and a
combination of access and data at a specific address. With the address break function, the
execution start point of a program containing a bug is detected and execution is branched to the
correcting program. Figure 4-1 shows a block diagram of the address break.
Interrupt
generation
control circuit
4.1

Register Descriptions

Address break has the following registers. For details on register addresses and register states
during each processing, refer to appendix B, Internal I/O Register.
• Address break control register(ABRKCR)
• Address break status register(ABRKSR)
• Break address register(BARH, BARL)
• Break data register(BDRH, BDRL)

Section 4 Address Break

Internal address bus
BARH
BDRH
Legend:
BARH, BARL: Break address register
BDRH, BDRL: Break data register
ABRKCR: Address break control register
ABRKSR: Address break status register
Figure 4-1 Block Diagram of an Address Break
Comparator
BARL
ABRKCR
ABRKSR
BDRL
Comparator
Interrupt
Rev. 1.0, 03/01, page 55 of 280