■Applicable devices
Operand
Bit
X, Y, M, L,
SM, F, B, SB,
FX, FY
(U/H)
(s1)
(s2)
(d1)
(d2)
■Control data
Operand: (s1)
Device
Item
+0
Completion status
+1
Number of write data
points
*1 This is the maximum setting range in a multiple CPU system consisting of two CPU modules.
It may be less than 8192 because the number of data points that can be written varies depending on the system configuration. (
Page 1401 Another CPU Module Access Instructions)
Processing details
• In a multiple CPU system, these instructions read the data in the device specified by (s2) in the host CPU module, by the
number of write data points specified by (s1)+1, and store it in the device specified by (d1) and later in another CPU module
(U/H).
Host CPU module
(write request source)
(s1)+1
• The following figure shows an outline of operation of the D(P).DDWR and M(P).DDWR instructions.
• Outline of operation of the D(P).DDWR instructions
Sequence scan
0
DP.DDWR instruction
Multiple CPU fixed scan
communication
0.888ms
(default)
Another CPU module
OFF
Completion device (d2)
Word
J\
T, ST, C, D, W,
U\G, J\,
SD, SW, FD,
U3E\(H)G
R, ZR, RD
Description
The completion status is stored.
• 0000H: Completed successfully
• Other than 0000H: Completed with an error (error code)
Specify the number of write data points in units of words.
Another CPU module
(read target)
(s2)
END
0
END
0
Execution of
the instruction
Request signal
Data transfer
Response signal
Accept
processing
Double word
Indirect
specification
Z
LT, LST,
LZ
LC
(d1)
END
0
END
0
Data transfer
ON
1 scan
12 MULTIPLE CPU DEDICATED INSTRUCTIONS
12.1 Another CPU Module Access Instructions
Constant
Others
(U)
K, H E
$
Setting range
Set by
System
*1
1 to 8192
User
END
0
END
OFF
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