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(2) Capture/compare register n0 (CR00, CR10)
CRn0 is a 16-bit register that functions as a capture register and as a compare register. Whether this register
functions as a capture or compare register is specified by using bit 0 (CRCn0) of the CRCn register.
(a) When using CRn0 as compare register
The value set to CRn0 is always compared with the count value of the TMn register. When the values of the
two coincide, an interrupt request (INTTMn0) is generated. When TMn is used as an interval timer, CRn0
can also be used as a register that holds the interval time.
(b) When using CRn0 as capture register
The valid edge of the TIn0 pin can be selected as a capture trigger. The valid edge for TIn0 is set by using
the PRMn register.
When the valid edge for TIn0 pin is specified as the capture trigger, refer to Table 7-2. When the valid edge
for TIn1 pin is specified as the capture trigger, refer to Table 7-3.
Table 7-2. Valid Edge of TIn0 Pin and Capture Trigger of CRn0
ESn01
ESn00
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both rising and falling edges
Remark n = 0, 1
Table 7-3. Valid Edge of TIn1 Pin and Capture Trigger of CRn0
ESn11
ESn10
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both rising and falling edges
Remark n = 0, 1
CRn0 is set by using a 16-bit memory manipulation instruction.
The value of this register is undefined when the RESET signal is input.
Caution Set CRn0 to a value other than 0000H. 1-pulse-count operation is disabled when used as an
event counter. However, if CRn0 is set to 0000H in free-running mode or in clear mode using the
TIn0 valid edge, an interrupt request (INTTMn0) is generated after an overflow (FFFFH).
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CHAPTER 7
TIMER/COUNTER FUNCTION
Valid Edge of TIn0 Pin
Valid Edge of TIn1 Pin
CRn0 Capture Trigger
Rising edge
Falling edge
Setting prohibited
No capture operation
CRn0 Capture Trigger
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
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