Chapter 4 Clock Generation Function; General - NEC Renesas V850/SC1 User Manual

4.1 General

The clock generator is a circuit that generates the clock pulses that are supplied to the CPU and peripheral
hardware. There are two types of system clock oscillators.
(1) Main clock oscillator
The V850/SC1 and V850/SC3 have an oscillation frequency of 4 to 20 MHz and the V850/SC2 4 to 18.87 MHz.
Oscillation can be stopped by setting the STOP mode or by setting the processor clock control register (PCC).
Oscillation is also stopped during a reset.
In IDLE mode, supplying the peripheral clock to the clock timer only is possible. Therefore, in IDLE mode, it is
possible to operate the clock timer without using the subclock oscillator.
Cautions 1. When the main clock oscillator is stopped by reset input or STOP mode setting, the
oscillation stabilization time is secured after the stop mode is canceled. This oscillation
stabilization time is set via the oscillation stabilization time select register (OSTS). The
watchdog timer is used to count the oscillation stabilization time.
2. If the main clock halt is released by clearing MCK to 0 after the main clock is stopped by
setting the MCK bit in the PCC register to 1, the oscillation stabilization time is not secured.
3. External clock input is disabled.
(2) Subclock oscillator
This circuit has an oscillation frequency of 32.768 kHz. Its oscillation is not stopped when the STOP mode is set,
nor when a reset is input.
When the subclock oscillator is not used, the FRC bit in the processor clock control register (PCC) can be set to
disable use of the internal feedback resistor. This enables a reduction in current consumption in the STOP
mode.
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CHAPTER 4 CLOCK GENERATION FUNCTION
User's Manual U15109EJ3V0UD